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8-46 Vol. 3A


The algorithm shown above can be adapted to work with earlier generations of single-core IA-32 processors that 
support Intel Hyper-Threading Technology and in situations that the deterministic cache parameter leaf is not 
supported (provided CPUID supports initial APIC ID). A reference code example is available (see Intel® 64 Archi-
tecture Processor Topology Enumeration




When a logical processor in an MP system (including multi-core processor or processors supporting Intel Hyper-
Threading Technology) is idle (no work to do) or blocked (on a lock or semaphore), additional management of the 
core execution engine resource can be accomplished by using the HLT (halt), PAUSE, or the MONITOR/MWAIT 

8.10.1 HLT 


The HLT instruction stops the execution of the logical processor on which it is executed and places it in a halted 
state until further notice (see the description of the HLT instruction in Chapter 3 of the Intel® 64 and IA-32 Archi-
tectures Software Developer’s Manual, Volume 2A
). When a logical processor is halted, active logical processors 
continue to have full access to the shared resources within the physical package. Here shared resources that were 
being used by the halted logical processor become available to active logical processors, allowing them to execute 
at greater efficiency. When the halted logical processor resumes execution, shared resources are again shared 
among all active logical processors. (See Section, â€śHalt Idle Logical Processors,” for more information 
about using the HLT instruction with processors supporting Intel Hyper-Threading Technology.)

8.10.2 PAUSE 


The PAUSE instruction can improves the performance of processors supporting Intel Hyper-Threading Technology 
when executing â€śspin-wait loops” and other routines where one thread is accessing a shared lock or semaphore in 
a tight polling loop. When executing a spin-wait loop, the processor can suffer a severe performance penalty when 
exiting the loop because it detects a possible memory order violation and flushes the core processor’s pipeline. The 
PAUSE instruction provides a hint to the processor that the code sequence is a spin-wait loop. The processor uses 
this hint to avoid the memory order violation and prevent the pipeline flush. In addition, the PAUSE instruction de-
pipelines the spin-wait loop to prevent it from consuming execution resources excessively and consume power 
needlessly. (See Section, â€śUse the PAUSE Instruction in Spin-Wait Loops,” for more information about 
using the PAUSE instruction with IA-32 processors supporting Intel Hyper-Threading Technology.)


Detecting Support MONITOR/MWAIT Instruction

Streaming SIMD Extensions 3 introduced two instructions (MONITOR and MWAIT) to help multithreaded software 
improve thread synchronization. In the initial implementation, MONITOR and MWAIT are available to software at 
ring 0. The instructions are conditionally available at levels greater than 0. Use the following steps to detect the 
availability of MONITOR and MWAIT:


Use CPUID to query the MONITOR bit (CPUID.1.ECX[3] = 1).


If CPUID indicates support, execute MONITOR inside a TRY/EXCEPT exception handler and trap for an 
exception. If an exception occurs, MONITOR and MWAIT are not supported at a privilege level greater than 0. 
See Example 8-23.