26-12 Vol. 3C

VM ENTRIES

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RFLAGS.
— Reserved bits 63:22 (bits 31:22 on processors that do not support Intel 64 architecture), bit 15, bit 5 and 

bit 3 must be 0 in the field, and reserved bit 1 must be 1.

— The VM flag (bit 17) must be 0 either if the “IA-32e mode guest” VM-entry control is 1 or if bit 0 in the CR0 

field (corresponding to CR0.PE) is 0.

1

— The IF flag (RFLAGS[bit 9]) must be 1 if the valid bit (bit 31) in the VM-entry interruption-information field 

is 1 and the interruption type (bits 10:8) is external interrupt.

26.3.1.5   Checks on Guest Non-Register State

The following checks are performed on fields in the guest-state area corresponding to non-register state:

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Activity state.
— The activity-state field must contain a value in the range 0 – 3, indicating an activity state supported by the 

implementation (see Section 24.4.2). Future processors may include support for other activity states. 
Software should read the VMX capability MSR IA32_VMX_MISC (see Appendix A.6) to determine what 
activity states are supported.

— The activity-state field must not indicate the HLT state if the DPL (bits 6:5) in the access-rights field for SS 

is not 0.

2

— The activity-state field must indicate the active state if the interruptibility-state field indicates blocking by 

either MOV-SS or by STI (if either bit 0 or bit 1 in that field is 1).

— If the valid bit (bit 31) in the VM-entry interruption-information field is 1, the interruption to be delivered 

(as defined by interruption type and vector) must not be one that would normally be blocked while a logical 
processor is in the activity state corresponding to the contents of the activity-state field. The following 
items enumerate the interruptions (as specified in the VM-entry interruption-information field) whose 
injection is allowed for the different activity states:

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Active. Any interruption is allowed.

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HLT. The only events allowed are the following:
— Those with interruption type external interrupt or non-maskable interrupt (NMI).
— Those with interruption type hardware exception and vector 1 (debug exception) or vector 18

(machine-check exception).

— Those with interruption type other event and vector 0 (pending MTF VM exit).
See Table 24-13 in Section 24.8.3 for details regarding the format of the VM-entry interruption-
information field.

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Shutdown. Only NMIs and machine-check exceptions are allowed.

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Wait-for-SIPI. No interruptions are allowed.

— The activity-state field must not indicate the wait-for-SIPI state if the “entry to SMM” VM-entry control is 1.

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Interruptibility state.
— The reserved bits (bits 31:5) must be 0.
— The field cannot indicate blocking by both STI and MOV SS (bits 0 and 1 cannot both be 1).
— Bit 0 (blocking by STI) must be 0 if the IF flag (bit 9) is 0 in the RFLAGS field.

1. Software can determine the number N by executing CPUID with 80000008H in EAX. The number of linear-address bits supported is 

returned in bits 15:8 of EAX.

1. If the capability MSR IA32_VMX_CR0_FIXED0 reports that CR0.PE must be 1 in VMX operation, bit 0 in the CR0 field must be 1 

unless the “unrestricted guest” VM-execution control and bit 31 of the primary processor-based VM-execution controls are both 1.

2. As noted in Section 24.4.1, SS.DPL corresponds to the logical processor’s current privilege level (CPL).