42-6 Vol. 3D
INTEL® SGX INTERACTIONS WITH IA32 AND INTEL® 64 ARCHITECTURE
The various consistency requirements are enforced at different times in the enclave's life cycle, and the exact
enforcement mechanisms are elaborated in Section 42.7.3 through Section 42.7.6.
On processors not supporting XSAVE, software should initialize XFRM to 0x3. On processors supporting XSAVE,
software should initialize XFRM to be a subset of XCR0 that would be present at the time of enclave execution.
Because bits 0 and 1 of XFRM must always be set, the use of Intel SGX requires that SSE be enabled (CR4.OSFXSR
= 1).
42.7.2.2 SECS.SSAFRAMESIZE
The SSAFRAMESIZE field in the SECS data structure specifies the number of pages which software allocated
1
for
each SSA frame, including both the GPRSGX area, MISC area, the XSAVE area (x87 and XMM states are stored in
the latter area), and optionally padding between the MISC and XSAVE area. The GPRSGX area must hold all the
general-purpose registers and additional Intel SGX specific information. The MISC area must hold the Miscella-
neous state as specified by SECS.MISCSELECT, the XSAVE area holds the set of processor extended states specified
by SECS.ATTRIBUTES.XFRM (see Section 38.9 for the layout of SSA and Section 42.7.3 for ECREATE's consistency
checks). The SSA is always in non-compacted format.
If the processor does not support XSAVE, the XSAVE area will always be 576 bytes; a copy of XFRM (which will be
set to 0x3) is saved at offset 512 on an AEX.
If the processor does support XSAVE, the length of the XSAVE area depends on SECS.ATTRIBUTES.XFRM. The
length would be equal to what CPUID.(EAX=0DH, ECX= 0):EBX would return if XCR0 were set to XFRM. The
following pseudo code illustrates how software can calculate this length using XFRM as the input parameter without
modifying XCR0:
offset = 576;
size_last_x = 0;
For x=2 to 63
IF (XFRM[x] != 0) Then
tmp_offset = CPUID.(EAX=0DH, ECX= x):EBX[31:0];
IF (tmp_offset >= offset + size_last_x) Then
offset = tmp_offset;
size_last_x = CPUID.(EAX=0DH, ECX= x):EAX[31:0];
FI;
FI;
EndFor
return (offset + size_last_x); (*
compute_xsave_size(XFRM), see “ECREATE—Create an SECS page in the Enclave
Where the non-zero bits in XFRM are a subset of non-zero bit fields in XCR0.
The size of the MISC region depends on the setting of SECS.MISCSELECT and can be calculated using the layout
information described in Section 38.9.2
42.7.2.3 XSAVE Area in SSA
The XSAVE area of an SSA frame begins at offset 0 of the frame.
42.7.2.4 MISC Area in SSA
The MISC area of an SSA frame is positioned immediately before the GPRSGX region.
42.7.2.5 SIGSTRUCT Fields
Intel SGX provides the flexibility for an enclave developer to choose the enclave's code path according to the
features that are enabled on the platform (e.g. optimize for AVX and fallback to SSE). See Section 42.7.1 for
details.
1. It is the responsibility of the enclave to actually allocate this memory.