Vol. 3A 9-5

PROCESSOR MANAGEMENT AND INITIALIZATION

9.1.2 

Processor Built-In Self-Test (BIST)

Hardware may request that the BIST be performed at power-up. The EAX register is cleared (0H) if the processor 
passes the BIST. A nonzero value in the EAX register after the BIST indicates that a processor fault was detected. 
If the BIST is not requested, the contents of the EAX register after a hardware reset is 0H. 
The overhead for performing a BIST varies between processor families. For example, the BIST takes approximately 
30 million processor clock periods to execute on the Pentium 4 processor. This clock count is model-specific; Intel 
reserves the right to change the number of periods for any Intel 64 or IA-32 processor, without notification.

9.1.3 

Model and Stepping Information

Following a hardware reset, the EDX register contains component identification and revision information (see 
Figure 9-2). For example, the model, family, and processor type returned for the first processor in the Intel 
Pentium 4 family is as follows: model (0000B), family (1111B), and processor type (00B). 

The stepping ID field contains a unique identifier for the processor’s stepping ID or revision level. The extended 
family and extended model fields were added to the IA-32 architecture in the Pentium 4 processors.

9.1.4 

First Instruction Executed

The first instruction that is fetched and executed following a hardware reset is located at physical address 
FFFFFFF0H. This address is 16 bytes below the processor’s uppermost physical address. The EPROM containing the 
software-initialization code must be located at this address. 
The address FFFFFFF0H is beyond the 1-MByte addressable range of the processor while in real-address mode. The 
processor is initialized to this starting address as follows. The CS register has two parts: the visible segment 
selector part and the hidden base address part. In real-address mode, the base address is normally formed by 
shifting the 16-bit segment selector value 4 bits to the left to produce a 20-bit base address. However, during a 
hardware reset, the segment selector in the CS register is loaded with F000H and the base address is loaded with 
FFFF0000H. The starting address is thus formed by adding the base address to the value in the EIP register (that 
is, FFFF0000 + FFF0H = FFFFFFF0H).
The first time the CS register is loaded with a new value after a hardware reset, the processor will follow the normal 
rule for address translation in real-address mode (that is, [CS base address = CS segment selector * 16]). To 
insure that the base address in the CS register remains unchanged until the EPROM based software-initialization 
code is completed, the code must not contain a far jump or far call or allow an interrupt to occur (which would 
cause the CS selector value to be changed).

9.2 

X87 FPU INITIALIZATION

Software-initialization code can determine the whether the processor contains an x87 FPU by using the CPUID 
instruction. The code must then initialize the x87 FPU and set flags in control register CR0 to reflect the state of the 
x87 FPU environment.

Figure 9-2.  Version Information in the EDX Register after Reset

31

12 11

8 7

4 3

0

EDX

Family (1111B for the Pentium 4 Processor Family)
Model (Beginning with 0000B)

13

14

Processor Type

Model

Family

Stepping

ID

15

Model

Extended

Extended

Family

16

19

20

27

28

Reserved