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35-304 Vol. 3C

MODEL-SPECIFIC REGISTERS (MSRS)

35.19  MSRS IN INTEL

®

 CORE

 SOLO AND INTEL

®

 CORE

 

DUO PROCESSORS

Model-specific registers (MSRs) for Intel Core Solo, Intel Core Duo processors, and Dual-core Intel Xeon processor 
LV are listed in Table 35-44. The column “Shared/Unique” applies to Intel Core Duo processor. “Unique” means 
each processor core has a separate MSR, or a bit field in an MSR governs only a core independently. “Shared” 
means the MSR or the bit field in an MSR address governs the operation of both processor cores.

107D0H

MSR_EMON_L3_CTR_CTL4

6

Shared

FSB Event Control and Counter Register 

(R/W) 
See Section 18.17, “Performance 

Monitoring on 64-bit Intel Xeon Processor 

MP with Up to 8-MByte L3 Cache” for 

details.

107D1H

MSR_EMON_L3_CTR_CTL5

6

Shared

FSB Event Control and Counter Register 

(R/W)

107D2H

MSR_EMON_L3_CTR_CTL6

6

Shared

FSB Event Control and Counter Register 

(R/W)

107D3H

MSR_EMON_L3_CTR_CTL7

6

Shared

FSB Event Control and Counter Register 

(R/W)

Table 35-44.  MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV

Register 

Address

Register Name

Shared/

Unique

Bit Description

 Hex

Dec

0H

0

P5_MC_ADDR

Unique

See Section 35.22, “MSRs in Pentium Processors,” and see 

Table 35-2.

1H

1

P5_MC_TYPE

Unique

See Section 35.22, “MSRs in Pentium Processors,” and see 

Table 35-2.

6H

6

IA32_MONITOR_FILTER_

SIZE

Unique

See Section 8.10.5, “Monitor/Mwait Address Range Determination,” 

and see Table 35-2.

10H

16

IA32_TIME_STAMP_

COUNTER

Unique

See Section 17.15, “Time-Stamp Counter,” and see Table 35-2.

17H

23

IA32_PLATFORM_ID

Shared

Platform ID (R) 
See Table 35-2.
The operating system can use this MSR to determine “slot” 

information for the processor and the proper microcode update to 

load.

1BH

27

IA32_APIC_BASE

Unique

See Section 10.4.4, “Local APIC Status and Location,” and see 

Table 35-2.

2AH

42

MSR_EBL_CR_POWERON

Shared

Processor Hard Power-On Configuration (R/W)
Enables and disables processor features; (R) indicates current 

processor configuration.

0

Reserved.

Table 35-43.  MSRs Unique to Intel® Xeon® Processor 7100 Series (Contd.)

Register Address

Register Name

Fields and Flags

Model Avail-

ability

Shared/

Unique

Bit Description