Vol. 3C 29-9

APIC VIRTUALIZATION AND VIRTUAL INTERRUPTS

If all of the items above are true, the processor performs self-IPI virtualization using the 8-bit vector in byte 0
of VICR_LO (Section 29.1.5).
If the “virtual-interrupt delivery” VM-execution control is 0, or if any of the items above are false, the
processor causes an APIC-write VM exit (Section 29.4.3.3).

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310H–313H (interrupt command — high). The processor clears bytes 2:0 of VICR_HI. No other virtualization or 
VM exit occurs.

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Any other page offset. The processor causes an APIC-write VM exit (Section 29.4.3.3).

APIC-write emulation takes priority over system-management interrupts (SMIs), INIT signals, and lower priority 
events. APIC-write emulation is not blocked if RFLAGS.IF = 0 or by the MOV SS, POP SS, or STI instructions.
If an operation causes a fault after a write access to the APIC-access page and before APIC-write emulation, and 
that fault is delivered without a VM exit, APIC-write emulation occurs after the fault is delivered and before the fault 
handler can execute. If an operation causes a VM exit (perhaps due to a fault) after a write access to the APIC-
access page and before APIC-write emulation, the APIC-write emulation does not occur.

29.4.3.3   APIC-Write VM Exits

In certain cases, VMM software must be invoked to complete the virtualization of a write access to the APIC-access 
page. In this case, APIC-write emulation causes an APIC-write VM exit. (Section 29.4.3.2 details the cases that 
causes APIC-write VM exits.)
APIC-write VM exits are invoked by APIC-write emulation, and APIC-write emulation occurs after an operation that 
performs a write access to the APIC-access page. Because of this, every APIC-write VM exit is trap-like: it occurs 
after completion of the operation containing the write access that caused the VM exit (for example, the value of 
CS:RIP saved in the guest-state area of the VMCS references the next instruction).
The basic exit reason for an APIC-write VM exit is “APIC write.” The exit qualification is the page offset of the write 
access that led to the VM exit.
As noted in Section 29.5, execution of WRMSR with ECX = 83FH (self-IPI MSR) can lead to an APIC-write VM exit 
if the “virtual-interrupt delivery” VM-execution control is 1. The exit qualification for such an APIC-write VM exit is 
3F0H.

29.4.4 Instruction-Specific 

Considerations

Certain instructions that use linear address may cause page faults even though they do not use those addresses to 
access memory. The APIC-virtualization features may affect these instructions as well:

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CLFLUSH, CLFLUSHOPT. With regard to faulting, the processor operates as if each of these instructions reads 
from the linear address in its source operand. If that address translates to one on the APIC-access page, the 
instruction may cause an APIC-access VM exit. If it does not, it will flush the corresponding cache line on the 
virtual-APIC page instead of the APIC-access page.

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ENTER. With regard to faulting, the processor operates if ENTER writes to the byte referenced by the final 
value of the stack pointer (even though it does not if its size operand is non-zero). If that value translates to an 
address on the APIC-access page, the instruction may cause an APIC-access VM exit. If it does not, it will cause 
the APIC-write emulation appropriate to the address’s page offset.

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MASKMOVQ and MAKSMOVDQU. Even if the instruction’s mask is zero, the processor may operate with 
regard to faulting as if MASKMOVQ or MASKMOVDQU writes to memory (the behavior is implementation-
specific). In such a situation, an APIC-access VM exit may occur.

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MONITOR. With regard to faulting, the processor operates as if MONITOR reads from the effective address in 
RAX. If the resulting linear address translates to one on the APIC-access page, the instruction may cause an 
APIC-access VM exit.

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 If it does not, it will monitor the corresponding address on the virtual-APIC page instead 

of the APIC-access page.

8. This chapter uses the notation RAX, RIP, RSP, RFLAGS, etc. for processor registers because most processors that support VMX oper-

ation also support Intel 64 architecture. For IA-32 processors, this notation refers to the 32-bit forms of those registers (EAX, EIP, 

ESP, EFLAGS, etc.). In a few places, notation such as EAX is used to refer specifically to lower 32 bits of the indicated register.