Vol. 3C 28-13

VMX SUPPORT FOR ADDRESS TRANSLATION

•

The EPT memory type is specified in bits 5:3 of the last EPT paging-structure entry: 0 = UC; 1 = WC; 4 = 
WT; 5 = WP; and 6 = WB. Other values are reserved and cause EPT misconfigurations (see Section 28.2.3).

•

If CR0.CD = 0, the effective memory type depends upon the value of bit 6 of the last EPT paging-structure 
entry:
— If the value is 0, the effective memory type is the combination of the EPT memory type and the PAT 

memory type specified in Table 11-7 in Section 11.5.2.2, using the EPT memory type in place of the MTRR 
memory type.

— If the value is 1, the memory type used for the access is the EPT memory type. The PAT memory type is 

ignored.

•

If CR0.CD = 1, the effective memory type is UC.

The MTRRs have no effect on the memory type used for an access to a guest-physical address.

28.3 

CACHING TRANSLATION INFORMATION

Processors supporting Intel

®

64 and IA-32 architectures may accelerate the address-translation process by 

caching on the processor data from the structures in memory that control that process. Such caching is discussed 
in Section 4.10, “Caching Translation Information” in the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 3A. The current section describes how this caching interacts with the VMX architecture.
The VPID and EPT features of the architecture for VMX operation augment this caching architecture. EPT defines 
the guest-physical address space and defines translations to that address space (from the linear-address space) 
and from that address space (to the physical-address space). Both features control the ways in which a logical 
processor may create and use information cached from the paging structures.
Section 28.3.1 describes the different kinds of information that may be cached. Section 28.3.2 specifies when such 
information may be cached and how it may be used. Section 28.3.3 details how software can invalidate cached 
information.

28.3.1 

Information That May Be Cached

Section 4.10, “Caching Translation Information” in Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 3A identifies two kinds of translation-related information that may be cached by a logical 
processor: translations, which are mappings from linear page numbers to physical page frames, and paging-
structure caches, which map the upper bits of a linear page number to information from the paging-structure 
entries used to translate linear addresses matching those upper bits.
The same kinds of information may be cached when VPIDs and EPT are in use. A logical processor may cache and 
use such information based on its function. Information with different functionality is identified as follows:

•

Linear mappings.

1

 There are two kinds:

— Linear translations. Each of these is a mapping from a linear page number to the physical page frame to 

which it translates, along with information about access privileges and memory typing.

— Linear paging-structure-cache entries. Each of these is a mapping from the upper portion of a linear 

address to the physical address of the paging structure used to translate the corresponding region of the 
linear-address space, along with information about access privileges. For example, bits 47:39 of a linear 
address would map to the address of the relevant page-directory-pointer table.

Linear mappings do not contain information from any EPT paging structure.

•

Guest-physical mappings.

2

 There are two kinds:

— Guest-physical translations. Each of these is a mapping from a guest-physical page number to the physical 

page frame to which it translates, along with information about access privileges and memory typing.

1. Earlier versions of this manual used the term “VPID-tagged” to identify linear mappings.
2. Earlier versions of this manual used the term “EPTP-tagged” to identify guest-physical mappings.