36-4 Vol. 3C
INTEL® PROCESSOR TRACE
as the CALL with matching stack depth), and the RET target is the instruction after that CALL, the RET
target may be “compressed”. In this case, only a single TNT bit of “taken” is generated instead of a Target
IP Packet. To ensure that the decoder will not be confused in cases of RET compression, only RETs that
correspond to CALLs which have been seen since the last PSB packet may be compressed in a given logical
processor. For details, see “Indirect Transfer Compression for Returns (RET)” in Section 36.4.2.2.
36.2.1.3 Far Transfer COFI
All operations that change the instruction pointer and are not near jumps are “far transfers”. This includes excep-
tions, interrupts, traps, TSX aborts, and instructions that do far transfers.
All far transfers will produce a Target IP (TIP) packet, which provides the destination IP address. For those far
transfers that cannot be inferred from the binary source (e.g., asynchronous events such as exceptions and inter-
rupts), the TIP will be preceded by a Flow Update packet (FUP), which provides the source IP address at which the
event was taken. Table 36-23 indicates exactly which IP will be included in the FUP generated by a far transfer.
36.2.2
Software Trace Instrumentation with PTWRITE
PTWRITE provides a mechanism by which software can instrument the Intel PT trace. PTWRITE is a ring3-acces-
sible instruction that can be passed a register or memory variable, see “PTWRITE - Write Data to a Processor Trace
Packet” in Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B for details. The contents of
that variable will be used as the payload for the PTW packet (see Table 36-40 “PTW Packet Definition”), inserted at
the time of PTWRITE retirement, assuming PTWRITE is enabled and all other filtering conditions are met. Decode
and analysis software will then be able to determine the meaning of the PTWRITE packet based on the IP of the
associated PTWRITE instruction.
PTWRITE is enabled via IA32_RTIT_CTL.PTWEn[12] (see Table 36-6). Optionally, the user can use
IA32_RTIT_CTL.FUPonPTW[5] to enable PTW packets to be followed by FUP packets containing the IP of the asso-
ciated PTWRITE instruction.
36.2.3
Power Event Tracing
Power Event Trace is a capability that exposes core- and thread-level sleep state and power down transition infor-
mation. When this capability is enabled, the trace will expose information about:
— Scenarios where software execution stops.
•
Due to sleep state entry, frequency change, or other powerdown.
•
Includes the IP, when in the tracing context.
— The requested and resolved hardware thread C-state.
•
Including indication of hardware autonomous C-state entry.
— The last and deepest core C-state achieved during a sleep session.
— The reason for C-state wake.
This information is in addition to the bus ratio (CBR) information provided by default after any powerdown, and the
timing information (TSC, TMA, MTC, CYC) provided during or after a powerdown state.
Power Event Trace is enabled via IA32_RTIT_CTL.PwrEvtEn[4].
36.2.4 Trace
Filtering
Intel Processor Trace provides filtering capabilities, by which the debug/profile tool can control what code is traced.
36.2.4.1 Filtering by Current Privilege Level (CPL)
Intel PT provides the ability to configure a logical processor to generate trace packets only when CPL = 0, when
CPL > 0, or regardless of CPL.