Vol. 3B 19-43

PERFORMANCE-MONITORING EVENTS

19.6 PERFORMANCE 

MONITORING 

EVENTS FOR 2ND GENERATION  

INTEL

®

CORE

™

 I7-2XXX, INTEL

®

CORE

™

 I5-2XXX, INTEL

®

CORE

™

 I3-2XXX 

PROCESSOR SERIES

2nd generation Intel

®

 Core™ i7-2xxx, Intel

®

 Core™ i5-2xxx, Intel

®

 Core™ i3-2xxx processor series, and Intel 

Xeon processor E3-1200 product family are based on the Intel microarchitecture code name Sandy Bridge. They 
support architectural performance-monitoring events listed in Table 19-1. Non-architectural performance-moni-
toring events in the processor core are listed in Table 19-13, Table 19-14, and Table 19-15. The events in Table 
19-13 apply to processors with CPUID signature of DisplayFamily_DisplayModel encoding with the following 
values: 06_2AH and 06_2DH. The events in Table 19-14 apply to processors with CPUID signature 06_2AH. The 
events in Table 19-15 apply to processors with CPUID signature 06_2DH. Fixed counters in the core PMU support 
the architecture events defined in Table 19-2.
Additional information on event specifics (e.g. derivative events using specific IA32_PERFEVTSELx modifiers, limi-
tations, special notes and recommendations) can be found at http://software.intel.com/en-us/forums/software-
tuning-performance-optimization-platform-monitoring.

Table 19-13.  Non-Architectural Performance Events In the Processor Core Common to 2nd Generation Intel® Core™ 

i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx Processor Series and Intel® Xeon® Processors E3 and E5 Family

Event

Num.

Umask

Value

Event Mask Mnemonic

Description

Comment

03H

01H

LD_BLOCKS.DATA_UNKNOWN Blocked loads due to store buffer blocks with 

unknown data. 

03H

02H

LD_BLOCKS.STORE_FORWARD Loads blocked by overlapping with store buffer that 

cannot be forwarded.

03H

08H

LD_BLOCKS.NO_SR

# of Split loads blocked due to resource not 

available. 

03H

10H

LD_BLOCKS.ALL_BLOCK

Number of cases where any load is blocked but has 

no DCU miss.

05H

01H

MISALIGN_MEM_REF.LOADS

Speculative cache-line split load uops dispatched to 

L1D.

05H

02H

MISALIGN_MEM_REF.STORES

Speculative cache-line split Store-address uops 

dispatched to L1D.

07H

01H

LD_BLOCKS_PARTIAL.ADDRES

S_ALIAS

False dependencies in MOB due to partial compare 

on address.

07H

08H

LD_BLOCKS_PARTIAL.ALL_STA

_BLOCK

The number of times that load operations are 

temporarily blocked because of older stores, with 

addresses that are not yet known. A load operation 

may incur more than one block of this type. 

08H

01H

DTLB_LOAD_MISSES.MISS_CA

USES_A_WALK

Misses in all TLB levels that cause a page walk of 

any page size.

08H

02H

DTLB_LOAD_MISSES.WALK_CO

MPLETED

Misses in all TLB levels that caused page walk 

completed of any size.

08H

04H

DTLB_LOAD_MISSES.WALK_DU

RATION

Cycle PMH is busy with a walk.

08H

10H

DTLB_LOAD_MISSES.STLB_HIT Number of cache load STLB hits. No page walk.

0DH

03H

INT_MISC.RECOVERY_CYCLES

Cycles waiting to recover after Machine Clears or 

JEClear. Set Cmask= 1.

Set Edge to count 

occurrences.

0DH

40H

INT_MISC.RAT_STALL_CYCLES Cycles RAT external stall is sent to IDQ for this 

thread.