Vol. 3A 4-19

PAGING

4.5 IA-32E 

PAGING

A logical processor uses IA-32e paging if CR0.PG = 1, CR4.PAE = 1, and IA32_EFER.LME = 1. With IA-32e paging, 
linear address are translated using a hierarchy of in-memory paging structures located using the contents of CR3. 
IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses.

1

 Although 52 bits corresponds to 4 

PBytes, linear addresses are limited to 48 bits; at most 256 TBytes of linear-address space may be accessed at any 
given time.
IA-32e paging uses a hierarchy of paging structures to produce a translation for a linear address. CR3 is used to 
locate the first paging-structure, the PML4 table. Use of CR3 with IA-32e paging depends on whether process-
context identifiers (PCIDs) have been enabled by setting CR4.PCIDE:

•

Table 4-12 illustrates how CR3 is used with IA-32e paging if CR4.PCIDE = 0.

•

Table 4-13 illustrates how CR3 is used with IA-32e paging if CR4.PCIDE = 1.

After software modifies the value of CR4.PCIDE, the logical processor immediately begins using CR3 as specified 
for the new value. For example, if software changes CR4.PCIDE from 1 to 0, the current PCID immediately changes 

1. If MAXPHYADDR < 52, bits in the range 51:MAXPHYADDR will be 0 in any physical address used by IA-32e paging. (The correspond-

ing bits are reserved in the paging-structure entries.) See Section 4.1.4 for how to determine MAXPHYADDR.

Table 4-12.  Use of CR3 with IA-32e Paging and CR4.PCIDE = 0

Bit 

Position(s)

Contents

2:0

Ignored

3 (PWT)

Page-level write-through; indirectly determines the memory type used to access the PML4 table during linear-

address translation (see Section 4.9.2)

4 (PCD)

Page-level cache disable; indirectly determines the memory type used to access the PML4 table during linear-address 

translation (see Section 4.9.2)

11:5

Ignored

M–1:12

Physical address of the 4-KByte aligned PML4 table used for linear-address translation

1

NOTES:

1. M is an abbreviation for MAXPHYADDR, which is at most 52; see Section 4.1.4.

63:M

Reserved (must be 0)

Table 4-13.  Use of CR3 with IA-32e Paging and CR4.PCIDE = 1

Bit 

Position(s)

Contents

11:0

PCID (see Section 4.10.1)

1

NOTES:

1. Section 4.9.2 explains how the processor determines the memory type used to access the PML4 table during linear-address transla-

tion with CR4.PCIDE = 1.

M–1:12

Physical address of the 4-KByte aligned PML4 table used for linear-address translation

2

2. M is an abbreviation for MAXPHYADDR, which is at most 52; see Section 4.1.4.

63:M

Reserved (must be 0)

3

3. See Section 4.10.4.1 for use of bit 63 of the source operand of the MOV to CR3 instruction.