Vol. 3A 11-33

MEMORY CACHE CONTROL

7. If the PGE flag is clear in control register CR4, flush all TLBs by executing a MOV from control register CR3 to 

another register and then a MOV from that register back to CR3.

8. Disable all range registers (by clearing the E flag in register MTRRdefType). If only variable ranges are being 

modified, software may clear the valid bits for the affected register pairs instead.

9. Update the MTRRs.
10. Enable all range registers (by setting the E flag in register MTRRdefType). If only variable-range registers were 

modified and their individual valid bits were cleared, then set the valid bits for the affected ranges instead.

11. Flush all caches and all TLBs a second time. (The TLB flush is required for Pentium 4, Intel Xeon, and P6 family 

processors. Executing the WBINVD instruction is not needed when using Pentium 4, Intel Xeon, and P6 family 
processors, but it may be needed in future systems.)

12. Enter the normal cache mode to re-enable caching. (Set the CD and NW flags in control register CR0 to 0.)
13. Set PGE flag in control register CR4, if cleared in Step 6 (above).
14. Wait for all processors to reach this point.
15. Enable interrupts.

11.11.9  Large Page Size Considerations

The MTRRs provide memory typing for a limited number of regions that have a 4 KByte granularity (the same gran-
ularity as 4-KByte pages). The memory type for a given page is cached in the processor’s TLBs. When using large 
pages (2 MBytes, 4 MBytes, or 1 GBytes), a single page-table entry covers multiple 4-KByte granules, each with a 
single memory type. Because the memory type for a large page is cached in the TLB, the processor can behave in 
an undefined manner if a large page is mapped to a region of memory that MTRRs have mapped with multiple 
memory types. 
Undefined behavior can be avoided by insuring that all MTRR memory-type ranges within a large page are of the 
same type. If a large page maps to a region of memory containing different MTRR-defined memory types, the PCD 
and PWT flags in the page-table entry should be set for the most conservative memory type for that range. For 
example, a large page used for memory mapped I/O and regular memory is mapped as UC memory. Alternatively, 
the operating system can map the region using multiple 4-KByte pages each with its own memory type. 
The requirement that all 4-KByte ranges in a large page are of the same memory type implies that large pages with 
different memory types may suffer a performance penalty, since they must be marked with the lowest common 
denominator memory type. The same consideration apply to 1 GByte pages, each of which may consist of multiple 
2-Mbyte ranges. 
The Pentium 4, Intel Xeon, and P6 family processors provide special support for the physical memory range from 0 
to 4 MBytes, which is potentially mapped by both the fixed and variable MTRRs. This support is invoked when a 
Pentium 4, Intel Xeon, or P6 family processor detects a large page overlapping the first 1 MByte of this memory 
range with a memory type that conflicts with the fixed MTRRs. Here, the processor maps the memory range as 
multiple 4-KByte pages within the TLB. This operation insures correct behavior at the cost of performance. To avoid 
this performance penalty, operating-system software should reserve the large page option for regions of memory 
at addresses greater than or equal to 4 MBytes.

11.12  PAGE ATTRIBUTE TABLE (PAT)

The Page Attribute Table (PAT) extends the IA-32 architecture’s page-table format to allow memory types to be 
assigned to regions of physical memory based on linear address mappings. The PAT is a companion feature to the 
MTRRs; that is, the MTRRs allow mapping of memory types to regions of the physical address space, where the PAT 
allows mapping of memory types to pages within the linear address space. The MTRRs are useful for statically 
describing memory types for physical ranges, and are typically set up by the system BIOS. The PAT extends the 
functions of the PCD and PWT bits in page tables to allow all five of the memory types that can be assigned with the 
MTRRs (plus one additional memory type) to also be assigned dynamically to pages of the linear address space.
The PAT was introduced to IA-32 architecture on the Pentium III processor. It is also available in the Pentium 4 and 
Intel Xeon processors.