Page 1420

35-140 Vol. 3C

MODEL-SPECIFIC REGISTERS (MSRS)

35.7

MSRS IN THE INTEL

XEON

PROCESSOR 5600 SERIES (BASED ON INTEL

MICROARCHITECTURE CODE NAME WESTMERE)

Intel

Xeon

Processor 5600 Series (based on Intel

microarchitecture code name Westmere) supports the MSR

interfaces listed in Table 35-13, Table 35-14, plus additional MSR listed in Table 35-16. These MSRs apply to Intel
Core i7, i5 and i3 processor family with CPUID signature DisplayFamily_DisplayModel of 06_25H and 06_2CH, see
Table 35-1.

Table 35-16. Additional MSRs Supported by Intel Processors

(Based on Intel® Microarchitecture Code Name Westmere)

Address

Scope

Bit Description

Hex

Dec

13CH

MSR_FEATURE_CONFIG

Core

AES Configuration (RW-L)
Privileged post-BIOS agent must provide a #GP handler to handle

unsuccessful read of this MSR.

1:0

AES Configuration (RW-L)
Upon a successful read of this MSR, the configuration of AES

instruction set availability is as follows:
11b: AES instructions are not available until next RESET.
otherwise, AES instructions are available.
Note, AES instruction set is not available if read is unsuccessful. If

the configuration is not 01b, AES instruction can be mis-configured

if a privileged agent unintentionally writes 11b.

63:2

Reserved.

1A7H

423

MSR_OFFCORE_RSP_1

Thread

Offcore Response Event Select Register (R/W)

1ADH

429

MSR_TURBO_RATIO_LIMIT

Package

Maximum Ratio Limit of Turbo Mode
RO if MSR_PLATFORM_INFO.[28] = 0,
RW if MSR_PLATFORM_INFO.[28] = 1

7:0

Package

Maximum Ratio Limit for 1C
Maximum turbo ratio limit of 1 core active.

15:8

Package

Maximum Ratio Limit for 2C
Maximum turbo ratio limit of 2 core active.