Vol. 3B 14-13

POWER AND THERMAL MANAGEMENT

Additional Guidelines

Set IA32_HWP_REQUEST.Energy_Performance_Preference as appropriate for the platform's current mode of oper-
ation. For example, a mobile platforms' setting may be towards performance preference when on AC power and 
more towards energy efficiency when on DC power.
The use of the Running Average Power Limit (RAPL) processor capability (see section 14.7.1) is highly recom-
mended when HWP is enabled. Use of IA32_HWP_Request.Maximum_Performance for thermal control is subject to 
limitations and can adversely impact the performance of other processor components e.g. Graphics
If default values deliver undesirable performance latency in response to events, the OS should set 
IA32_HWP_REQUEST. Activity_Window to a low (non zero) value and 
IA32_HWP_REQUEST.Energy_Performance_Preference towards performance (0) for the event duration.
Similarly, for “real-time” threads, set IA32_HWP_REQUEST.Energy_Performance_Preference towards performance 
(0) and IA32_HWP_REQUEST. Activity_Window to a low value, e.g. 01H, for the duration of their execution.
When executing low priority work that may otherwise cause the hardware to deliver high performance, set 
IA32_HWP_REQUEST. Activity_Window to a longer value and reduce the 
IA32_HWP_Request.Maximum_Performance value as appropriate to control energy efficiency. Adjustments to 
IA32_HWP_REQUEST.Energy_Performance_Preference may also be necessary.

14.5 

HARDWARE DUTY CYCLING (HDC)

Intel processors may contain support for Hardware Duty Cycling (HDC), which enables the processor to autono-
mously force its components inside the physical package into idle state. For example, the processor may selectively 
force only the processor cores into an idle state. 
HDC is disabled by default on processors that support it. System software can dynamically enable or disable HDC 
to force one or more components into an idle state or wake up those components previously forced into an idle 
state. Forced Idling (and waking up) of multiple components in a physical package can be done with one WRMSR 
to a packaged-scope MSR from any logical processor within the same package. 
HDC does not delay events such as timer expiration, but it may affect the latency of short (less than 1 msec) soft-
ware threads, e.g. if a thread is forced to idle state just before completion and entering a “natural idle”.
HDC forced idle operation can be thought of as operating at a lower effective frequency. The effective average 
frequency computed by software will include the impact of HDC forced idle. 
The primary use of HDC is enable system software to manage low active workloads to increase the package level 
C6 residency. Additionally, HDC can lower the effective average frequency in case or power or thermal limitation. 
When HDC forces a logical processor, a processor core or a physical package to enter an idle state, its C-State is set 
to C3 or deeper. The deep “C-states” referred to in this section are processor-specific C-states.

14.5.1 

Hardware Duty Cycling Programming Interfaces 

The programming interfaces provided by HDC include the following:

•

The CPUID instruction allows software to discover the presence of HDC support in an Intel processor. Specifi-
cally, execute CPUID instruction with EAX=06H as input, bit 13 of EAX indicates the processor’s support of the 
following aspects of HDC.
— Availability of HDC baseline resource, CPUID.06H:EAX[bit 13]: If this bit is set, HDC provides the following 

architectural MSRs: IA32_PKG_HDC_CTL, IA32_PM_CTL1, and the IA32_THREAD_STALL MSRs.

•

Additionally, HDC may provide several non-architectural MSR. 

Table 14-2.  Architectural and non-Architecture MSRs Related to HDC

Address Architec

tural

Register Name

Description