Vol. 3B 17-35

DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES

Additional information is saved if an exception or interrupt occurs in conjunction with a branch instruction. If a 
branch instruction generates a trap type exception, two branch records are stored in the LBR stack: a branch 
record for the branch instruction followed by a branch record for the exception.
If a branch instruction is immediately followed by an interrupt, a branch record is stored in the LBR stack for the 
branch instruction followed by a record for the interrupt. 

17.11.3  Last Exception Records

The Pentium 4, Intel Xeon, Pentium M, Intel

®

 Core™ Solo, Intel

®

 Core™ Duo, Intel

®

 Core™2 Duo, Intel

®

 Core™ i7 

and Intel

®

 Atom™ processors provide two MSRs (the MSR_LER_TO_LIP and the MSR_LER_FROM_LIP MSRs) that 

duplicate the functions of the LastExceptionToIP and LastExceptionFromIP MSRs found in the P6 family processors. 
The MSR_LER_TO_LIP and MSR_LER_FROM_LIP MSRs contain a branch record for the last branch that the 
processor took prior to an exception or interrupt being generated.

17.12  LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING (INTEL® CORE™ 

SOLO AND INTEL® CORE™

 

DUO PROCESSORS)

Intel Core Solo and Intel Core Duo processors provide last branch interrupt and exception recording. This capability 
is almost identical to that found in Pentium 4 and Intel Xeon processors. There are differences in the stack and in 
some MSR names and locations. 
Note the following:

•

IA32_DEBUGCTL MSR — Enables debug trace interrupt, debug trace store, trace messages enable, 
performance monitoring breakpoint flags, single stepping on branches, and last branch. IA32_DEBUGCTL MSR 
is located at register address 01D9H. 
See Figure 17-14 for the layout and the entries below for a description of the flags:
— LBR (last branch/interrupt/exception) flag (bit 0) — When set, the processor records a running trace 

of the most recent branches, interrupts, and/or exceptions taken by the processor (prior to a debug 
exception being generated) in the last branch record (LBR) stack. For more information, see the “Last 
Branch Record (LBR) Stack” below.

— BTF (single-step on branches) flag (bit 1) — When set, the processor treats the TF flag in the EFLAGS 

register as a “single-step on branches” flag rather than a “single-step on instructions” flag. This mechanism 

Figure 17-13.  LBR MSR Branch Record Layout for the Pentium 4 

and Intel Xeon Processor Family

63

From Linear Address

0

To Linear Address

63

From Linear Address

0

0

63

To Linear Address

32 - 31

MSR_LASTBRANCH_0 through MSR_LASTBRANCH_3 

CPUID Family 0FH, Models 0H-02H

Reserved

CPUID Family 0FH, Model 03H-04H

Reserved

MSR_LASTBRANCH_0_FROM_IP through MSR_LASTBRANCH_15_FROM_IP

32 - 31

32 - 31

MSR_LASTBRANCH_0_TO_IP through MSR_LASTBRANCH_15_TO_IP