10-42 Vol. 3A

ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)

which was not initialized at reset, is not architecturally defined across this transition and system software 
should explicitly initialize those programmable APIC registers. 

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to the disabled state by setting EN to 0 (resulting EN=0, EXTD= 0).

The result of an INIT in the xAPIC state places the APIC in the state with EN= 1, EXTD= 0. The state of the local 
APIC ID register is preserved (the 8-bit xAPIC ID is in the upper 8 bits of the APIC ID register). All the other APIC 
registers are initialized as a result of INIT. 
A reset in this state places the APIC in the state with EN= 1, EXTD= 0. The state of the local APIC ID register is 
initialized as described in Section 10.12.5.1. All the other APIC registers are initialized described in Section 
10.12.5.1. 

x2APIC Transitions From x2APIC Mode

From the x2APIC mode, the only valid x2APIC transition using IA32_APIC_BASE is to the state where the x2APIC 
is disabled by setting EN to 0 and EXTD to 0. The x2APIC ID (32 bits) and the legacy local xAPIC ID (8 bits) are 
preserved across this transition. A transition from the x2APIC mode to xAPIC mode is not valid, and the corre-
sponding WRMSR to the IA32_APIC_BASE MSR causes a general-protection exception. 
A reset in this state places the x2APIC in xAPIC mode. All APIC registers (including the local APIC ID register) are 
initialized as described in Section 10.12.5.1. 
An INIT in this state keeps the x2APIC in the x2APIC mode. The state of the local APIC ID register is preserved (all 
32 bits). However, all the other APIC registers are initialized as a result of the INIT transition.

x2APIC Transitions From Disabled Mode

From the disabled state, the only valid x2APIC transition using IA32_APIC_BASE is to the xAPIC mode (EN= 1, 
EXTD = 0). Thus the only means to transition from x2APIC mode to xAPIC mode is a two-step process: 

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first transition from x2APIC mode to local APIC disabled mode (EN= 0, EXTD = 0),

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followed by another transition from disabled mode to xAPIC mode (EN= 1, EXTD= 0).

Consequently, all the APIC register states in the x2APIC, except for the x2APIC ID (32 bits), are not preserved 
across mode transitions. 
A reset in the disabled state places the x2APIC in the xAPIC mode. All APIC registers (including the local APIC ID 
register) are initialized as described in Section 10.12.5.1. 
An INIT in the disabled state keeps the x2APIC in the disabled state.

State Changes From xAPIC Mode to x2APIC Mode

After APIC register states have been initialized by software in xAPIC mode, a transition from xAPIC mode to x2APIC 
mode does not affect most of the APIC register states, except the following:

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The Logical Destination Register is not preserved.

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Any APIC ID value written to the memory-mapped local APIC ID register is not preserved.

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The high half of the Interrupt Command Register is not preserved. 

10.12.6  Routing of Device Interrupts in x2APIC Mode

The x2APIC architecture is intended to work with all existing IOxAPIC units as well as all PCI and PCI Express (PCIe) 
devices that support the capability for message-signaled interrupts (MSI). Support for x2APIC modifies only the 
following:

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the local APIC units;

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the interconnects joining IOxAPIC units to the local APIC units; and

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the interconnects joining MSI-capable PCI and PCIe devices to the local APIC units.

No modifications are required to MSI-capable PCI and PCIe devices. Similarly, no modifications are required to 
IOxAPIC units. This made possible through use of the interrupt-remapping architecture specified in the Intel

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