10-10 Vol. 3A
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
For the P6 family and Pentium processors, the local APIC ID field in the local APIC ID register is 4 bits. Encodings
0H through EH can be used to uniquely identify 15 different processors connected to the APIC bus. For the Pentium
4 and Intel Xeon processors, the xAPIC specification extends the local APIC ID field to 8 bits. These can be used to
identify up to 255 processors in the system.
10.4.7
Local APIC State
The following sections describe the state of the local APIC and its registers following a power-up or reset, after the
local APIC has been software disabled, following an INIT reset, and following an INIT-deassert message.
x2APIC will introduce 32-bit ID; see Section 10.12.
10.4.7.1 Local APIC State After Power-Up or Reset
Following a power-up or reset of the processor, the state of local APIC and its registers are as follows:
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The following registers are reset to all 0s:
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IRR, ISR, TMR, ICR, LDR, and TPR
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Timer initial count and timer current count registers
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Divide configuration register
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The DFR register is reset to all 1s.
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The LVT register is reset to 0s except for the mask bits; these are set to 1s.
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The local APIC version register is not affected.
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The local APIC ID register is set to a unique APIC ID. (Pentium and P6 family processors only). The Arb ID
register is set to the value in the APIC ID register.
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The spurious-interrupt vector register is initialized to 000000FFH. By setting bit 8 to 0, software disables the
local APIC.
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If the processor is the only processor in the system or it is the BSP in an MP system (see Section 8.4.1, “BSP
and AP Processors”); the local APIC will respond normally to INIT and NMI messages, to INIT# signals and to
STPCLK# signals. If the processor is in an MP system and has been designated as an AP; the local APIC will
respond the same as for the BSP. In addition, it will respond to SIPI messages. For P6 family processors only,
an AP will not respond to a STPCLK# signal.
10.4.7.2 Local APIC State After It Has Been Software Disabled
When the APIC software enable/disable flag in the spurious interrupt vector register has been explicitly cleared (as
opposed to being cleared during a power up or reset), the local APIC is temporarily disabled (see Section 10.4.3,
“Enabling or Disabling the Local APIC”). The operation and response of a local APIC while in this software-disabled
state is as follows:
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The local APIC will respond normally to INIT, NMI, SMI, and SIPI messages.
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Pending interrupts in the IRR and ISR registers are held and require masking or handling by the CPU.
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The local APIC can still issue IPIs. It is software’s responsibility to avoid issuing IPIs through the IPI mechanism
and the ICR register if sending interrupts through this mechanism is not desired.
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The reception of any interrupt or transmission of any IPIs that are in progress when the local APIC is disabled
are completed before the local APIC enters the software-disabled state.
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The mask bits for all the LVT entries are set. Attempts to reset these bits will be ignored.
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(For Pentium and P6 family processors) The local APIC continues to listen to all bus messages in order to keep
its arbitration ID synchronized with the rest of the system.
10.4.7.3 Local APIC State After an INIT Reset (“Wait-for-SIPI” State)
An INIT reset of the processor can be initiated in either of two ways: