Vol. 3A 8-37

MULTIPLE-PROCESSOR MANAGEMENT

8.9.3.1  

Hierarchical ID of Logical Processors with x2APIC ID

Table 8-4 shows an example of possible x2APIC ID assignments for a dual processor system that support x2APIC. 
Each physical package providing four processor cores, and each processor core also supporting Intel Hyper-
Threading Technology. Note that the x2APIC ID need not be contiguous in the system.

8.9.4 

Algorithm for Three-Level Mappings of APIC_ID

Software can gather the initial APIC_IDs for each logical processor supported by the operating system at runtime

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and extract identifiers corresponding to the three levels of sharing topology (package, core, and SMT). The three-
level algorithms below focus on a non-clustered MP system for simplicity. They do not assume APIC IDs are contig-
uous or that all logical processors on the platform are enabled.
Intel supports multi-threading systems where all physical processors report identical values in CPUID leaf 0BH, 
CPUID.1:EBX[23:16]), CPUID.4

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:EAX[31:26], and CPUID.4

11

:EAX[25:14]. The algorithms below assume the 

target system has symmetry across physical package boundaries with respect to the number of logical processors 
per package, number of cores per package, and cache topology within a package.
The extraction algorithm (for three-level mappings from an APIC ID) uses the general procedure depicted in 
Example 8-18, and is supplemented by more detailed descriptions on the derivation of topology enumeration 
parameters for extraction bit masks:
1. Detect hardware multi-threading support in the processor.

Table 8-4.  Example of Possible x2APIC ID Assignment in a System that has Two Physical Processors Supporting 

x2APIC and Intel Hyper-Threading Technology 

x2APIC ID

Package ID

Core ID

SMT ID

0H

0H

0H

0H

1H

0H

0H

1H

2H

0H

1H

0H

3H

0H

1H

1H

4H

0H

2H

0H

5H

0H

2H

1H

6H

0H

3H

0H

7H

0H

3H

1H

10H

1H

0H

0H

11H

1H

0H

1H

12H

1H

1H

0H

13H

1H

1H

1H

14H

1H

2H

0H

15H

1H

2H

1H

16H

1H

3H

0H

17H

1H

3H

1H

9. As noted in Section 8.6 and Section 8.9.3, the number of logical processors supported by the OS at runtime may be less than the 

total number logical processors available in the platform hardware.

10. Maximum number of addressable ID for processor cores in a physical processor is obtained by executing CPUID with EAX=4 and a 

valid ECX index, The ECX index start at 0.

11. Maximum number addressable ID for processor cores sharing the target cache level is obtained by executing CPUID with EAX = 4 

and the ECX index corresponding to the target cache level.