Vol. 3A 6-43

INTERRUPT AND EXCEPTION HANDLING

Interrupt 16—x87 FPU Floating-Point Error (#MF)

Exception Class

Fault.

Description

Indicates that the x87 FPU has detected a floating-point error. The NE flag in the register CR0 must be set for an 
interrupt 16 (floating-point error exception) to be generated. (See Section 2.5, “Control Registers,” for a detailed 
description of the NE flag.)

NOTE

SIMD floating-point exceptions (#XM) are signaled through interrupt 19. 

While executing x87 FPU instructions, the x87 FPU detects and reports six types of floating-point error conditions:

•

Invalid operation (#I)
— Stack overflow or underflow (#IS)
— Invalid arithmetic operation (#IA)

•

Divide-by-zero (#Z)

•

Denormalized operand (#D)

•

Numeric overflow (#O)

•

Numeric underflow (#U)

•

Inexact result (precision) (#P)

Each of these error conditions represents an x87 FPU exception type, and for each of exception type, the x87 FPU 
provides a flag in the x87 FPU status register and a mask bit in the x87 FPU control register. If the x87 FPU detects 
a floating-point error and the mask bit for the exception type is set, the x87 FPU handles the exception automati-
cally by generating a predefined (default) response and continuing program execution. The default responses have 
been designed to provide a reasonable result for most floating-point applications.
If the mask for the exception is clear and the NE flag in register CR0 is set, the x87 FPU does the following:
1. Sets the necessary flag in the FPU status register.
2. Waits until the next “waiting” x87 FPU instruction or WAIT/FWAIT instruction is encountered in the program’s 

instruction stream.

3. Generates an internal error signal that cause the processor to generate a floating-point exception (#MF).
Prior to executing a waiting x87 FPU instruction or the WAIT/FWAIT instruction, the x87 FPU checks for pending 
x87 FPU floating-point exceptions (as described in step 2 above). Pending x87 FPU floating-point exceptions are 
ignored for “non-waiting” x87 FPU instructions, which include the FNINIT, FNCLEX, FNSTSW, FNSTSW AX, FNSTCW, 
FNSTENV, and FNSAVE instructions. Pending x87 FPU exceptions are also ignored when executing the state 
management instructions FXSAVE and FXRSTOR.
All of the x87 FPU floating-point error conditions can be recovered from. The x87 FPU floating-point-error exception 
handler can determine the error condition that caused the exception from the settings of the flags in the x87 FPU 
status word. See “Software Exception Handling” in Chapter 8 of the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 1, for more information on handling x87 FPU floating-point exceptions.

Exception Error Code

None. The x87 FPU provides its own error information.

Saved Instruction Pointer

The saved contents of CS and EIP registers point to the floating-point or WAIT/FWAIT instruction that was about to 
be executed when the floating-point-error exception was generated. This is not the faulting instruction in which the 
error condition was detected. The address of the faulting instruction is contained in the x87 FPU instruction pointer