Vol. 3B 22-9

ARCHITECTURE COMPATIBILITY

When porting software written to run on a 16-bit IA-32 math coprocessor to a 32-bit x87 FPU, uninitialized memory 
locations that contain QNaNs should be changed to SNaNs to cause the x87 FPU or math coprocessor to fault when 
uninitialized memory locations are referenced.

22.18.5.2   Pseudo-zero, Pseudo-NaN, Pseudo-infinity, and Unnormal Formats

The 32-bit x87 FPUs neither generate nor support the pseudo-zero, pseudo-NaN, pseudo-infinity, and unnormal 
formats. Whenever they encounter them in an arithmetic operation, they raise an invalid-operation exception. The 
16-bit IA-32 math coprocessors define and support special handling for these formats. Support for these formats 
was dropped to conform with IEEE Standard 754 for Binary Floating-Point Arithmetic.
This change should not impact software ported from 16-bit IA-32 math coprocessors to 32-bit x87 FPUs. The 32-
bit x87 FPUs do not generate these formats, and therefore will not encounter them unless software explicitly loads 
them in the data registers. The only affect may be in how software handles the tags in the tag word (see also: 
Section 22.18.4, “x87 FPU Tag Word”).

22.18.6 Floating-Point 

Exceptions

This section identifies the implementation differences in exception handling for floating-point instructions in the 
various x87 FPUs and math coprocessors.

22.18.6.1   Denormal Operand Exception (#D)

When the denormal operand exception is masked, the 32-bit x87 FPUs automatically normalize denormalized 
numbers when possible; whereas, the 16-bit IA-32 math coprocessors return a denormal result. A program written 
to run on a 16-bit IA-32 math coprocessor that uses the denormal exception solely to normalize denormalized 
operands is redundant when run on the 32-bit x87 FPUs. If such a program is run on 32-bit x87 FPUs, performance 
can be improved by masking the denormal exception. Floating-point programs run faster when the FPU performs 
normalization of denormalized operands.
The denormal operand exception is not raised for transcendental instructions and the FXTRACT instruction on the 
16-bit IA-32 math coprocessors. This exception is raised for these instructions on the 32-bit x87 FPUs. The excep-
tion handlers ported to these latter processors need to be changed only if the handlers gives special treatment to 
different opcodes.

22.18.6.2   Numeric Overflow Exception (#O)

On the 32-bit x87 FPUs, when the numeric overflow exception is masked and the rounding mode is set to chop 
(toward 0), the result is the largest positive or smallest negative number. The 16-bit IA-32 math coprocessors do 
not signal the overflow exception when the masked response is not ∞; that is, they signal overflow only when the 

rounding control is not set to round to 0. If rounding is set to chop (toward 0), the result is positive or negative ∞. 

Under the most common rounding modes, this difference has no impact on existing software. 
If rounding is toward 0 (chop), a program on a 32-bit x87 FPU produces, under overflow conditions, a result that is 
different in the least significant bit of the significand, compared to the result on a 16-bit IA-32 math coprocessor. 
The reason for this difference is IEEE Standard 754 compatibility.
When the overflow exception is not masked, the precision exception is flagged on the 32-bit x87 FPUs. When the 
result is stored in the stack, the significand is rounded according to the precision control (PC) field of the FPU 
control word or according to the opcode. On the 16-bit IA-32 math coprocessors, the precision exception is not 
flagged and the significand is not rounded. The impact on existing software is that if the result is stored on the 
stack, a program running on a 32-bit x87 FPU produces a different result under overflow conditions than on a 16-
bit IA-32 math coprocessor. The difference is apparent only to the exception handler. This difference is for IEEE 
Standard 754 compatibility.