Vol. 3B 22-27

ARCHITECTURE COMPATIBILITY

22.27.1  Software Visible Differences Between the Local APIC and the 82489DX

The following features in the local APIC features differ from those found in the 82489DX external APIC:

•

When the local APIC is disabled by clearing the APIC software enable/disable flag in the spurious-interrupt 
vector MSR, the state of its internal registers are unaffected, except that the mask bits in the LVT are all set to 
block local interrupts to the processor. Also, the local APIC ceases accepting IPIs except for INIT, SMI, NMI, and 
start-up IPIs. In the 82489DX, when the local unit is disabled, all the internal registers including the IRR, ISR 
and TMR are cleared and the mask bits in the LVT are set. In this state, the 82489DX local unit will accept only 
the reset deassert message.

•

In the local APIC, NMI and INIT (except for INIT deassert) are always treated as edge triggered interrupts, 
even if programmed otherwise. In the 82489DX, these interrupts are always level triggered. 

•

In the local APIC, IPIs generated through the ICR are always treated as edge triggered (except INIT Deassert). 
In the 82489DX, the ICR can be used to generate either edge or level triggered IPIs. 

•

In the local APIC, the logical destination register supports 8 bits; in the 82489DX, it supports 32 bits. 

•

In the local APIC, the APIC ID register is 4 bits wide; in the 82489DX, it is 8 bits wide.

•

The remote read delivery mode provided in the 82489DX and local APIC for Pentium processors is not 
supported in the local APIC in the Pentium 4, Intel Xeon, and P6 family processors.

•

For the 82489DX, in the lowest priority delivery mode, all the target local APICs specified by the destination 
field participate in the lowest priority arbitration. For the local APIC, only those local APICs which have free 
interrupt slots will participate in the lowest priority arbitration.

22.27.2  New Features Incorporated in the Local APIC for the P6 Family

 

and Pentium 

Processors

The local APIC in the Pentium and P6 family processors have the following new features not found in the 82489DX 
external APIC.

•

Cluster addressing is supported in logical destination mode.

•

Focus processor checking can be enabled/disabled.

•

Interrupt input signal polarity can be programmed for the LINT0 and LINT1 pins.

•

An SMI IPI is supported through the ICR and I/O redirection table.

•

An error status register is incorporated into the LVT to log and report APIC errors.

In the P6 family processors, the local APIC incorporates an additional LVT register to handle performance moni-
toring counter interrupts.

22.27.3  New Features Incorporated in the Local APIC of the Pentium 4 and Intel Xeon 

Processors

The local APIC in the Pentium 4 and Intel Xeon processors has the following new features not found in the P6 family 
and Pentium processors and in the 82489DX.

•

The local APIC ID is extended to 8 bits.

•

An thermal sensor register is incorporated into the LVT to handle thermal sensor interrupts. 

•

The the ability to deliver lowest-priority interrupts to a focus processor is no longer supported.

•

The flat cluster logical destination mode is not supported.

22.28  TASK SWITCHING AND TSS

This section identifies the implementation differences of task switching, additions to the TSS and the handling of 
TSSs and TSS segment selectors.