17-16 Vol. 3B

DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES

Registers (MSRs)” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C for model-
specific MSR addresses). 

•

Last Branch Record (LBR) Stack — The LBR consists of N pairs of MSRs (N is listed in the LBR stack size 
column of Table 17-4) that store source and destination address of recent branches (see Figure 17-3): 
— MSR_LASTBRANCH_0_FROM_IP (address is model specific) through the next consecutive (N-1) MSR 

address store source addresses.

— MSR_LASTBRANCH_0_TO_IP (address is model specific ) through the next consecutive (N-1) MSR address 

store destination addresses.

•

Last Branch Record Top-of-Stack (TOS) Pointer — The lowest significant M bits of the TOS Pointer MSR 
(MSR_LASTBRANCH_TOS, address is model specific) contains an M-bit pointer to the MSR in the LBR stack that 
contains the most recent branch, interrupt, or exception recorded. The valid range of the M-bit POS pointer is 
given in Table 17-4.

17.4.8.1   LBR Stack and Intel® 64 Processors 

LBR MSRs are 64-bits. In 64-bit mode, last branch records store the full address. Outside of 64-bit mode, the upper 
32-bits of branch addresses will be stored as 0. 

Software should query an architectural MSR IA32_PERF_CAPABILITIES[5:0] about the format of the address that 

is stored in the LBR stack. Four formats are defined by the following encoding:

— 000000B (32-bit record format) — Stores 32-bit offset in current CS of respective source/destination,
— 000001B (64-bit LIP record format) — Stores 64-bit linear address of respective source/destination,
— 000010B (64-bit EIP record format) — Stores 64-bit offset (effective address) of respective 

source/destination.

— 000011B (64-bit EIP record format) and Flags — Stores 64-bit offset (effective address) of respective 

source/destination. Misprediction info is reported in the upper bit of 'FROM' registers in the LBR stack. See 
LBR stack details below for flag support and definition.

— 000100B (64-bit EIP record format), Flags and TSX — Stores 64-bit offset (effective address) of 

respective source/destination. Misprediction and TSX info are reported in the upper bits of ‘FROM’ registers 
in the LBR stack. 

— 000101B (64-bit EIP record format), Flags, TSX, LBR_INFO — Stores 64-bit offset (effective 

address) of respective source/destination. Misprediction, TSX, and elapsed cycles since the last LBR update 
are reported in the LBR_INFO MSR stack. 

— 000110B (64-bit EIP record format), Flags, Cycles — Stores 64-bit linear address (CS.Base + 

effective address) of respective source/destination. Misprediction info is reported in the upper bits of 
'FROM' registers in the LBR stack. Elapsed cycles since the last LBR update are reported in the upper 16 bits 
of the 'TO' registers in the LBR stack (see Section 17.6). 

Processor’s support for the architectural MSR IA32_PERF_CAPABILITIES is provided by 
CPUID.01H:ECX[PERF_CAPAB_MSR] (bit 15).

Figure 17-4.  64-bit Address Layout of LBR MSR 

63

Source Address

0

0

63

Destination Address

MSR_LASTBRANCH_0_FROM_IP through MSR_LASTBRANCH_(N-1)_FROM_IP

MSR_LASTBRANCH_0_TO_IP through MSR_LASTBRANCH_(N-1)_TO_IP