Vol. 3B 18-105

PERFORMANCE MONITORING

18.17.3  Incrementing the Time-Stamp Counter

The time-stamp counter increments when the clock signal on the system bus is active and when the sleep pin is not 
asserted. The counter value can be read with the RDTSC instruction.
The time-stamp counter and the non-sleep clockticks count may not agree in all cases and for all processors. See 
Section 17.15, “Time-Stamp Counter,” for more information on counter operation.

18.17.4  Non-Halted Reference Clockticks

Software can use either processor-specific performance monitor events (for example: CPU_CLK_UNHALTED.BUS 
on processors based on the Intel Core microarchitecture, and equivalent event specifications on the Intel Core Duo 
and Intel Core Solo processors) to count non-halted reference clockticks.
These events count reference clock cycles whenever the specified processor is not halted. The counter counts 
reference cycles associated with a fixed-frequency clock source irrespective of P-state, TM2, or frequency transi-
tions that may occur to the processor.

18.17.5  Cycle Counting and Opportunistic Processor Operation

As a result of the state transitions due to opportunistic processor performance operation (see Chapter 14, “Power 
and Thermal Management”), a logical processor or a processor core can operate at frequency different from the 
Processor Base frequency. 
The following items are expected to hold true irrespective of when opportunistic processor operation causes state 
transitions:

•

The time stamp counter operates at a fixed-rate frequency of the processor.

•

The IA32_MPERF counter increments at a fixed frequency irrespective of any transitions caused by opportu-
nistic processor operation.

•

The IA32_FIXED_CTR2 counter increments at the same TSC frequency irrespective of any transitions caused 
by opportunistic processor operation.

•

The Local APIC timer operation is unaffected by opportunistic processor operation.

•

The TSC, IA32_MPERF, and IA32_FIXED_CTR2 operate at close to the maximum non-turbo frequency, which is 
equal to the product of scalable bus frequency and maximum non-turbo ratio. 

For processors based on Intel Core microarchitecture, the scalable bus frequency is encoded in the bit field 
MSR_FSB_FREQ[2:0] at (0CDH), see Chapter 35, “Model-Specific Registers (MSRs)”. The maximum resolved bus 
ratio can be read from the following bit field:

•

If XE operation is disabled, the maximum resolved bus ratio can be read in MSR_PLATFORM_ID[12:8]. It 
corresponds to the Processor Base frequency.

•

IF XE operation is enabled, the maximum resolved bus ratio is given in MSR_PERF_STAT[44:40], it corresponds 
to the maximum XE operation frequency configured by BIOS.

XE operation of an Intel 64 processor is implementation specific. XE operation can be enabled only by BIOS. If 
MSR_PERF_STAT[31] is set, XE operation is enabled. The MSR_PERF_STAT[31] field is read-only.

18.18 IA32_PERF_CAPABILITIES 

MSR 

ENUMERATION

The layout of IA32_PERF_CAPABILITIES MSR is shown in Figure 18-49, it provides enumeration of a variety of 
interfaces:

•

IA32_PERF_CAPABILITIES.LBR_FMT[bits 5:0]: encodes the LBR format, details are described in Section 
17.4.8.1.

•

IA32_PERF_CAPABILITIES.PEBSTrap[6]: Trap/Fault-like indicator of PEBS recording assist, see Section 
18.4.4.2.