2-22 Vol. 3A
SYSTEM ARCHITECTURE OVERVIEW
2.8.1
Loading and Storing System Registers
The GDTR, LDTR, IDTR, and TR registers each have a load and store instruction for loading data into and storing
data from the register:
•
LGDT (Load GDTR Register) — Loads the GDT base address and limit from memory into the GDTR register.
•
SGDT (Store GDTR Register) — Stores the GDT base address and limit from the GDTR register into memory.
•
LIDT (Load IDTR Register) — Loads the IDT base address and limit from memory into the IDTR register.
•
SIDT (Store IDTR Register) — Stores the IDT base address and limit from the IDTR register into memory.
•
LLDT (Load LDTR Register) — Loads the LDT segment selector and segment descriptor from memory into
the LDTR. (The segment selector operand can also be located in a general-purpose register.)
•
SLDT (Store LDTR Register) — Stores the LDT segment selector from the LDTR register into memory or a
general-purpose register.
•
LTR (Load Task Register) — Loads segment selector and segment descriptor for a TSS from memory into the
task register. (The segment selector operand can also be located in a general-purpose register.)
•
STR (Store Task Register) — Stores the segment selector for the current task TSS from the task register into
memory or a general-purpose register.
The LMSW (load machine status word) and SMSW (store machine status word) instructions operate on bits 0
through 15 of control register CR0. These instructions are provided for compatibility with the 16-bit Intel 286
processor. Programs written to run on 32-bit IA-32 processors should not use these instructions. Instead, they
should access the control register CR0 using the MOV CR instruction.
The CLTS (clear TS flag in CR0) instruction is provided for use in handling a device-not-available exception (#NM)
that occurs when the processor attempts to execute a floating-point instruction when the TS flag is set. This
instruction allows the TS flag to be cleared after the x87 FPU context has been saved, preventing further #NM
exceptions. See Section 2.5, “Control Registers,” for more information on the TS flag.
The control registers (CR0, CR1, CR2, CR3, CR4, and CR8) are loaded using the MOV instruction. The instruction
loads a control register from a general-purpose register or stores the content of a control register in a general-
purpose register.
2.8.2
Verifying of Access Privileges
The processor provides several instructions for examining segment selectors and segment descriptors to determine
if access to their associated segments is allowed. These instructions duplicate some of the automatic access rights
and type checking done by the processor, thus allowing operating-system or executive software to prevent excep-
tions from being generated.
The ARPL (adjust RPL) instruction adjusts the RPL (requestor privilege level) of a segment selector to match that of
the program or procedure that supplied the segment selector. See Section 5.10.4, “Checking Caller Access Privi-
leges (ARPL Instruction)” for a detailed explanation of the function and use of this instruction. Note that ARPL is not
supported in 64-bit mode.
NOTES:
1. Useful to application programs running at a CPL of 1 or 2.
2. The TSD and PCE flags in control register CR4 control access to these instructions by application programs running at a CPL of 3.
3. These instructions were introduced into the IA-32 Architecture with the Pentium processor.
4. This instruction was introduced into the IA-32 Architecture with the Pentium Pro processor and the Pentium processor with MMX technol-
ogy.
5. This instruction is not supported in 64-bit mode.
6. Application uses XGETBV to query which set of processor extended states are enabled.
7. RDTSCP is introduced in Intel Core i7 processor.
Table 2-3. Summary of System Instructions (Contd.)
Instruction
Description
Useful to
Application?
Protected from
Application?