Vol. 3C 34-3

SYSTEM MANAGEMENT MODE

ated on the system bus and the multiplexed status signal EXF4 is asserted each time a bus transaction is generated 
while the processor is in SMM. For the Pentium and Intel486 processors, the SMIACT# pin is asserted.
An SMI has a greater priority than debug exceptions and external interrupts. Thus, if an NMI, maskable hardware 
interrupt, or a debug exception occurs at an instruction boundary along with an SMI, only the SMI is handled. 
Subsequent SMI requests are not acknowledged while the processor is in SMM. The first SMI interrupt request that 
occurs while the processor is in SMM (that is, after SMM has been acknowledged to external hardware) is latched 
and serviced when the processor exits SMM with the RSM instruction. The processor will latch only one SMI while 
in SMM.
See Section 34.5 for a detailed description of the execution environment when in SMM.

34.3.2 

Exiting From SMM

The only way to exit SMM is to execute the RSM instruction. The RSM instruction is only available to the SMI 
handler; if the processor is not in SMM, attempts to execute the RSM instruction result in an invalid-opcode excep-
tion (#UD) being generated.
The RSM instruction restores the processor’s context by loading the state save image from SMRAM back into the 
processor’s registers. The processor then returns an SMIACK transaction on the system bus and returns program 
control back to the interrupted program.
Upon successful completion of the RSM instruction, the processor signals external hardware that SMM has been 
exited. For the P6 family processors, an SMI acknowledge transaction is generated on the system bus and the 
multiplexed status signal EXF4 is no longer generated on bus cycles. For the Pentium and Intel486 processors, the 
SMIACT# pin is deserted.
If the processor detects invalid state information saved in the SMRAM, it enters the shutdown state and generates 
a special bus cycle to indicate it has entered shutdown state. Shutdown happens only in the following situations:

•

A reserved bit in control register CR4 is set to 1 on a write to CR4. This error should not happen unless SMI 
handler code modifies reserved areas of the SMRAM saved state map (see Section 34.4.1). CR4 is saved in the 
state map in a reserved location and cannot be read or modified in its saved state.

•

An illegal combination of bits is written to control register CR0, in particular PG set to 1 and PE set to 0, or NW 
set to 1 and CD set to 0.

•

CR4.PCIDE would be set to 1 and IA32_EFER.LMA to 0.

•

(For the Pentium and Intel486 processors only.) If the address stored in the SMBASE register when an RSM 
instruction is executed is not aligned on a 32-KByte boundary. This restriction does not apply to the P6 family 
processors.

In the shutdown state, Intel processors stop executing instructions until a RESET#, INIT# or NMI# is asserted. 
While Pentium family processors recognize the SMI# signal in shutdown state, P6 family and Intel486 processors 
do not. Intel does not support using SMI# to recover from shutdown states for any processor family; the response 
of processors in this circumstance is not well defined. On Pentium 4 and later processors, shutdown will inhibit 
INTR and A20M but will not change any of the other inhibits. On these processors, NMIs will be inhibited if no action 
is taken in the SMI handler to uninhibit them (see Section 34.8).
If the processor is in the HALT state when the SMI is received, the processor handles the return from SMM slightly 
differently (see Section 34.10). Also, the SMBASE address can be changed on a return from SMM (see Section 
34.11).

34.4 SMRAM

Upon entering SMM, the processor switches to a new address space. Because paging is disabled upon entering 
SMM, this initial address space maps all memory accesses to the low 4 GBytes of the processor's physical address 
space. The SMI handler's critical code and data reside in a memory region referred to as system-management RAM 
(SMRAM). The processor uses a pre-defined region within SMRAM to save the processor's pre-SMI context. SMRAM 
can also be used to store system management information (such as the system configuration and specific informa-
tion about powered-down devices) and OEM-specific information.