25-10 Vol. 3C

VMX NON-ROOT OPERATION

— If ECX contains 808H (indicating the TPR MSR), 80BH (the EOI MSR), or 83FH (self-IPI MSR), instruction 

behavior may modified if the “virtualize x2APIC mode” VM-execution control is 1; see Section 29.5.

•

XRSTORS. Behavior of the XRSTORS instruction is determined first by the setting of the “enable 
XSAVES/XRSTORS” VM-execution control:
— If the “enable XSAVES/XRSTORS” VM-execution control is 0, XRSTORS causes an invalid-opcode exception 

(#UD).

— If the “enable XSAVES/XRSTORS” VM-execution control is 1, treatment is based on the value of the XSS-

exiting bitmap (see Section 24.6.19):

•

XRSTORS causes a VM exit if any bit is set in the logical-AND of the following three values: EDX:EAX, 

the IA32_XSS MSR, and the XSS-exiting bitmap.

•

Otherwise, XRSTORS operates normally.

•

XSAVES. Behavior of the XSAVES instruction is determined first by the setting of the “enable 
XSAVES/XRSTORS” VM-execution control:
— If the “enable XSAVES/XRSTORS” VM-execution control is 0, XSAVES causes an invalid-opcode exception 

(#UD).

— If the “enable XSAVES/XRSTORS” VM-execution control is 1, treatment is based on the value of the XSS-

exiting bitmap (see Section 24.6.19):

•

XSAVES causes a VM exit if any bit is set in the logical-AND of the following three values: EDX:EAX, the 

IA32_XSS MSR, and the XSS-exiting bitmap.

•

Otherwise, XSAVES operates normally.

25.4 

OTHER CHANGES IN VMX NON-ROOT OPERATION

Treatments of event blocking and of task switches differ in VMX non-root operation as described in the following 
sections.

25.4.1 Event 

Blocking

Event blocking is modified in VMX non-root operation as follows:

•

If the “external-interrupt exiting” VM-execution control is 1, RFLAGS.IF does not control the blocking of 
external interrupts. In this case, an external interrupt that is not blocked for other reasons causes a VM exit 
(even if RFLAGS.IF = 0).

•

If the “external-interrupt exiting” VM-execution control is 1, external interrupts may or may not be blocked by 
STI or by MOV SS (behavior is implementation-specific).

•

If the “NMI exiting” VM-execution control is 1, non-maskable interrupts (NMIs) may or may not be blocked by 
STI or by MOV SS (behavior is implementation-specific).

25.4.2 

Treatment of Task Switches

Task switches are not allowed in VMX non-root operation. Any attempt to effect a task switch in VMX non-root oper-
ation causes a VM exit. However, the following checks are performed (in the order indicated), possibly resulting in 
a fault, before there is any possibility of a VM exit due to task switch:
1. If a task gate is being used, appropriate checks are made on its P bit and on the proper values of the relevant 

privilege fields. The following cases detail the privilege checks performed:
a. If CALL, INT n, or JMP accesses a task gate in IA-32e mode, a general-protection exception occurs.
b. If CALL, INT n, INT3, INTO, or JMP accesses a task gate outside IA-32e mode, privilege-levels checks are 

performed on the task gate but, if they pass, privilege levels are not checked on the referenced task-state 
segment (TSS) descriptor.