31-12 Vol. 3C

VIRTUAL-MACHINE MONITOR PROGRAMMING CONSIDERATIONS

processor's current VMCS should be modified by any logical processor or DMA. Before updating one of these struc-
tures, the VMM must ensure that no logical processor whose current VMCS references the structure is in VMX non-
root operation. 
If a VMM uses multiple VMCS with each VMCS using separate external structures, and these structures must be 
kept synchronized, the VMM must apply the same care to updating these structures.

31.8.5 CPUID 

Emulation

CPUID reports information that is used by OS and applications to detect hardware features. It also provides multi-
threading/multi-core configuration information. For example, MP-aware OSs rely on data reported by CPUID to 
discover the topology of logical processors in a platform (see Section 8.9, “Programming Considerations for Hard-
ware Multi-Threading Capable Processors,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
Volume 3A). 
If a VMM is to support asymmetric allocation of logical processor resources to guest OSs that are MP aware, then 
the VMM must emulate CPUID for its guests. The emulation of CPUID by the VMM must ensure the guest’s view of 
CPUID leaves are consistent with the logical processor allocation committed by the VMM to each guest OS.

31.9 

32-BIT AND 64-BIT GUEST ENVIRONMENTS

For the most part, extensions provided by VMX to support virtualization are orthogonal to the extensions provided 
by Intel 64 architecture. There are considerations that impact VMM designs. These are described in the following 
subsections.

31.9.1 

Operating Modes of Guest Environments

For Intel 64 processors, VMX operation supports host and guest environments that run in IA-32e mode or without 
IA-32e mode. VMX operation also supports host and guest environments on IA-32 processors. 
A VMM entering VMX operation while IA-32e mode is active is considered to be an IA-32e mode host. A VMM 
entering VMX operation while IA-32e mode is not activated or not available is referred to as a 32-bit VMM. The type 
of guest operations such VMMs support are summarized in Table 31-1.

A VM exit may occur to an IA-32e mode guest in either 64-bit sub-mode or compatibility sub-mode of IA-32e 
mode. VMMs may resume guests in either mode. The sub-mode in which an IA-32e mode guest resumes VMX non-
root operation is determined by the attributes of the code segment which experienced the VM exit. If CS.L = 1, the 
guest is executing in 64-bit mode; if CS.L = 0, the guest is executing in compatibility mode (see Section 31.9.5).
Not all of an IA-32e mode VMM must run in 64-bit mode. While some parts of an IA-32e mode VMM must run in 64-
bit mode, there are only a few restrictions preventing a VMM from executing in compatibility mode. The most 
notable restriction is that most VMX instructions cause exceptions when executed in compatibility mode. 

31.9.2 

Handling Widths of VMCS Fields

Individual VMCS control fields must be accessed using VMREAD or VMWRITE instructions. Outside of 64-Bit mode, 
VMREAD and VMWRITE operate on 32 bits of data. The widths of VMCS control fields may vary depending on 
whether a processor supports Intel 64 architecture.

Table 31-1.  Operating Modes for Host and Guest Environments

Capability

Guest Operation 

in IA-32e mode

Guest Operation 

Not Requiring IA-32e Mode

IA-32e mode VMM

Yes

Yes

32-bit VMM

Not supported

Yes