Vol. 3A 2-19

SYSTEM ARCHITECTURE OVERVIEW

priority interrupt to be blocked. A value of 0 means all interrupts are enabled. This field is available in 64-
bit mode. A value of 15 means all interrupts will be disabled.

2.5.1 

CPUID Qualification of Control Register Flags

Not all flags in control register CR4 are implemented on all processors. With the exception of the PCE flag, they can 
be qualified with the CPUID instruction to determine if they are implemented on the processor before they are 
used. 
The CR8 register is available on processors that support Intel 64 architecture.

2.6 

EXTENDED CONTROL REGISTERS (INCLUDING XCR0)

If CPUID.01H:ECX.XSAVE[bit 26] is 1, the processor supports one or more extended control registers (XCRs). 
Currently, the only such register defined is XCR0. This register specifies the set of processor state components for 
which the operating system provides context management, e.g. x87 FPU state, SSE state, AVX state. The OS 
programs XCR0 to reflect the features for which it provides context management.

Software can access XCR0 only if CR4.OSXSAVE[bit 18] = 1. (This bit is also readable as 
CPUID.01H:ECX.OSXSAVE[bit 27].) Software can use CPUID leaf function 0DH to enumerate the bits in XCR0 that 
the processor supports (see CPUID instruction in Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
Volume 2A). Each supported state component is represented by a bit in XCR0. System software enables state 
components by loading an appropriate bit mask value into XCR0 using the XSETBV instruction.
As each bit in XCR0 (except bit 63) corresponds to a processor state component, XCR0 thus provides support for 
up to 63 sets of processor state components. Bit 63 of XCR0 is reserved for future expansion and will not represent 
a processor state component.
Currently, XCR0 defines support for the following state components:

•

XCR0.X87 (bit 0): This bit 0 must be 1. An attempt to write 0 to this bit causes a #GP exception.

•

XCR0.SSE (bit 1): If 1, the XSAVE feature set can be used to manage MXCSR and the XMM registers (XMM0-
XMM15 in 64-bit mode; otherwise XMM0-XMM7). 

•

XCR0.AVX (bit 2): If 1, AVX instructions can be executed and the XSAVE feature set can be used to manage the 
upper halves of the YMM registers (YMM0-YMM15 in 64-bit mode; otherwise YMM0-YMM7).

•

XCR0.BNDREG (bit 3): If 1, MPX instructions can be executed and the XSAVE feature set can be used to 
manage the bounds registers BND0–BND3. 

Figure 2-8.  XCR0

63

Reserved for XCR0 bit vector expansion
Reserved / Future processor extended states

2 1 0

AVX state

1

Reserved (must be 0)

x87 FPU/MMX state (must be 1)

SSE state

9

PKRU state

5

6

7

Hi16_ZMM state
ZMM_Hi256 state
Opmask state

4 3

BNDCSR state
BNDREG state