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Vol. 3A 4-37


The access rights from the paging-structure entries used to translate linear addresses with the page number 
(see Section 4.6):
— The logical-AND of the R/W flags.
— The logical-AND of the U/S flags.
— The logical-OR of the XD flags (necessary only if IA32_EFER.NXE = 1).
— The protection key (necessary only with IA-32e paging and CR4.PKE = 1).

Attributes from a paging-structure entry that identifies the final page frame for the page number (either a PTE 
or a paging-structure entry in which the PS flag is 1):
— The dirty flag (see Section 4.8).
— The memory type (see Section 4.9).

(TLB entries may contain other information as well. A processor may implement multiple TLBs, and some of these 
may be for special purposes, e.g., only for instruction fetches. Such special-purpose TLBs may not contain some of 
this information if it is not necessary. For example, a TLB used only for instruction fetches need not contain infor-
mation about the R/W and dirty flags.)
As noted in Section 4.10.1, any TLB entries created by a logical processor are associated with the current PCID.
Processors need not implement any TLBs. Processors that do implement TLBs may invalidate any TLB entry at any 
time. Software should not rely on the existence of TLBs or on the retention of TLB entries.   Details of TLB Use

Because the TLBs cache entries only for linear addresses with translations, there can be a TLB entry for a page 
number only if the P flag is 1 and the reserved bits are 0 in each of the paging-structure entries used to translate 
that page number. In addition, the processor does not cache a translation for a page number unless the accessed 
flag is 1 in each of the paging-structure entries used during translation; before caching a translation, the processor 
sets any of these accessed flags that is not already 1.
The processor may cache translations required for prefetches and for accesses that are a result of speculative 
execution that would never actually occur in the executed code path.
If the page number of a linear address corresponds to a TLB entry associated with the current PCID, the processor 
may use that TLB entry to determine the page frame, access rights, and other attributes for accesses to that linear 
address. In this case, the processor may not actually consult the paging structures in memory. The processor may 
retain a TLB entry unmodified even if software subsequently modifies the relevant paging-structure entries in 
memory. See Section for how software can ensure that the processor uses the modified paging-structure 
If the paging structures specify a translation using a page larger than 4 KBytes, some processors may cache 
multiple smaller-page TLB entries for that translation. Each such TLB entry would be associated with a page 
number corresponding to the smaller page size (e.g., bits 47:12 of a linear address with IA-32e paging), even 
though part of that page number (e.g., bits 20:12) is part of the offset with respect to the page specified by the 
paging structures. The upper bits of the physical address in such a TLB entry are derived from the physical address 
in the PDE used to create the translation, while the lower bits come from the linear address of the access for which 
the translation is created. There is no way for software to be aware that multiple translations for smaller pages 
have been used for a large page. For example, an execution of INVLPG for a linear address on such a page invali-
dates any and all smaller-page TLB entries for the translation of any linear address on that page.
If software modifies the paging structures so that the page size used for a 4-KByte range of linear addresses 
changes, the TLBs may subsequently contain multiple translations for the address range (one for each page size). 
A reference to a linear address in the address range may use any of these translations. Which translation is used 
may vary from one execution to another, and the choice may be implementation-specific.   Global Pages

The Intel-64 and IA-32 architectures also allow for global pages when the PGE flag (bit 7) is 1 in CR4. If the G flag 
(bit 8) is 1 in a paging-structure entry that maps a page (either a PTE or a paging-structure entry in which the PS 
flag is 1), any TLB entry cached for a linear address using that paging-structure entry is considered to be global