Vol. 3C 34-1

CHAPTER 34

SYSTEM MANAGEMENT MODE

This chapter describes aspects of IA-64 and IA-32 architecture used in system management mode (SMM).
SMM provides an alternate operating environment that can be used to monitor and manage various system 
resources for more efficient energy usage, to control system hardware, and/or to run proprietary code. It was 
introduced into the IA-32 architecture in the Intel386 SL processor (a mobile specialized version of the Intel386 
processor). It is also available in the Pentium M, Pentium 4, Intel Xeon, P6 family, and Pentium and Intel486 
processors (beginning with the enhanced versions of the Intel486 SL and Intel486 processors). 

34.1 

SYSTEM MANAGEMENT MODE OVERVIEW

SMM is a special-purpose operating mode provided for handling system-wide functions like power management, 
system hardware control, or proprietary OEM-designed code. It is intended for use only by system firmware, not by 
applications software or general-purpose systems software. The main benefit of SMM is that it offers a distinct and 
easily isolated processor environment that operates transparently to the operating system or executive and soft-
ware applications. 
When SMM is invoked through a system management interrupt (SMI), the processor saves the current state of the 
processor (the processor’s context), then switches to a separate operating environment defined by a new address 
space. The system management software executive (SMI handler) starts execution in that environment, and the 
critical code and data of the SMI handler reside in a physical memory region (SMRAM) within that address space. 
While in SMM, the processor executes SMI handler code to perform operations such as powering down unused disk 
drives or monitors, executing proprietary code, or placing the whole system in a suspended state. When the SMI 
handler has completed its operations, it executes a resume (RSM) instruction. This instruction causes the processor 
to reload the saved context of the processor, switch back to protected or real mode, and resume executing the 
interrupted application or operating-system program or task.
The following SMM mechanisms make it transparent to applications programs and operating systems:

•

The only way to enter SMM is by means of an SMI.

•

The processor executes SMM code in a separate address space that can be made inaccessible from the other 
operating modes.

•

Upon entering SMM, the processor saves the context of the interrupted program or task.

•

All interrupts normally handled by the operating system are disabled upon entry into SMM.

•

The RSM instruction can be executed only in SMM.

Section 34.3 describes transitions into and out of SMM. The execution environment after entering SMM is in real-
address mode with paging disabled (CR0.PE = CR0.PG = 0). In this initial execution environment, the SMI handler 
can address up to 4 GBytes of memory and can execute all I/O and system instructions. Section 34.5 describes in 
detail the initial SMM execution environment for an SMI handler and operation within that environment. The SMI 
handler may subsequently switch to other operating modes while remaining in SMM.

NOTES

Software developers should be aware that, even if a logical processor was using the physical-
address extension (PAE) mechanism (introduced in the P6 family processors) or was in IA-32e 
mode before an SMI, this will not be the case after the SMI is delivered. This is because delivery of 
an SMI disables paging (see Table 34-4). (This does not apply if the dual-monitor treatment of SMIs 
and SMM is active; see Section 34.15.)

34.1.1 

System Management Mode and VMX Operation

Traditionally, SMM services system management interrupts and then resumes program execution (back to the soft-
ware stack consisting of executive and application software; see Section 34.2 through Section 34.13).