Vol. 3C 27-11

VM EXITS

(#BR; generated by BOUND) and invalid opcode exceptions (#UD) generated by UD2 are hardware 
exceptions.

— Bit 11 is set to 1 if the VM exit is caused by a hardware exception that would have delivered an error code 

on the stack. This bit is always 0 if the VM exit occurred while the logical processor was in real-address 
mode (CR0.PE=0).

1

 If bit 11 is set to 1, the error code is placed in the VM-exit interruption error code (see 

below).

— Bit 12 is undefined in any of the following cases:

•

If the “NMI exiting” VM-execution control is 1 and the “virtual NMIs” VM-execution control is 0.

•

If the VM exit sets the valid bit in the IDT-vectoring information field (see Section 27.2.3).

•

If the VM exit is due to a double fault (the interruption type is hardware exception and the vector is 8).

Otherwise, bit 12 is defined as follows:

•

If the “virtual NMIs” VM-execution control is 0, the VM exit is due to a fault on the IRET instruction 
(other than a debug exception for an instruction breakpoint), and blocking by NMI (see Table 24-3) was 
in effect before execution of IRET, bit 12 is set to 1.

•

If the “virtual NMIs” VM-execution control is 1, the VM exit is due to a fault on the IRET instruction 
(other than a debug exception for an instruction breakpoint), and virtual-NMI blocking was in effect 
before execution of IRET, bit 12 is set to 1.

•

For all other relevant VM exits, bit 12 is cleared to 0.

2

— Bits 30:13 are always set to 0.
— Bit 31 is always set to 1.
For other VM exits (including those due to external interrupts when the “acknowledge interrupt on exit” 
VM-exit control is 0), the field is marked invalid (by clearing bit 31) and the remainder of the field is undefined.

•

VM-exit interruption error code.
— For VM exits that set both bit 31 (valid) and bit 11 (error code valid) in the VM-exit interruption-information 

field, this field receives the error code that would have been pushed on the stack had the event causing the 
VM exit been delivered normally through the IDT. The EXT bit is set in this field exactly when it would be set 
normally. For exceptions that occur during the delivery of double fault (if the IDT-vectoring information field 
indicates a double fault), the EXT bit is set to 1, assuming that (1) that the exception would produce an 
error code normally (if not incident to double-fault delivery) and (2) that the error code uses the EXT bit 
(not for page faults, which use a different format).

— For other VM exits, the value of this field is undefined.

27.2.3 

Information for VM Exits During Event Delivery

Section 24.9.3 defined fields containing information for VM exits that occur while delivering an event through the 
IDT and as a result of any of the following cases:

3

•

A fault occurs during event delivery and causes a VM exit (because the bit associated with the fault is set to 1 
in the exception bitmap).

•

A task switch is invoked through a task gate in the IDT. The VM exit occurs due to the task switch only after the 
initial checks of the task switch pass (see Section 25.4.2).

•

Event delivery causes an APIC-access VM exit (see Section 29.4).

1. If the capability MSR IA32_VMX_CR0_FIXED0 reports that CR0.PE must be 1 in VMX operation, a logical processor cannot be in real-

address mode unless the “unrestricted guest” VM-execution control and bit 31 of the primary processor-based VM-execution con-

trols are both 1.

2. The conditions imply that, if the “NMI exiting” VM-execution control is 0 or the “virtual NMIs” VM-execution control is 1, bit 12  is 

always cleared to 0 by VM exits due to debug exceptions.

3. This includes the case in which a VM exit occurs while delivering a software interrupt (INT n) through the 16-bit IVT (interrupt vec-

tor table) that is used in virtual-8086 mode with virtual-machine extensions (if RFLAGS.VM = CR4.VME = 1).