Vol. 3C 36-21
INTEL® PROCESSOR TRACE
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Processors that enumerate support for 2 ranges support:
IA32_RTIT_ADDR0_A, IA32_RTIT_ADDR0_B
IA32_RTIT_ADDR1_A, IA32_RTIT_ADDR1_B
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Processors that enumerate support for 3 ranges support:
IA32_RTIT_ADDR0_A, IA32_RTIT_ADDR0_B
IA32_RTIT_ADDR1_A, IA32_RTIT_ADDR1_B
IA32_RTIT_ADDR2_A, IA32_RTIT_ADDR2_B
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Processors that enumerate support for 4 ranges support:
IA32_RTIT_ADDR0_A, IA32_RTIT_ADDR0_B
IA32_RTIT_ADDR1_A, IA32_RTIT_ADDR1_B
IA32_RTIT_ADDR2_A, IA32_RTIT_ADDR2_B
IA32_RTIT_ADDR3_A, IA32_RTIT_ADDR3_B
Each register has a single 64-bit field that holds a linear address value. Writes must ensure that the address is
properly sign-extended, otherwise a #GP fault will result.
36.2.7.6 IA32_RTIT_CR3_MATCH MSR
The IA32_RTIT_CR3_MATCH register is compared against CR3 when IA32_RTIT_CTL.CR3Filter is 1. Bits 63:5 hold
the CR3 address value to match, bits 4:0 are reserved to 0. For more details on CR3 filtering and the treatment of
this register, see Section 36.2.4.2.
This MSR can be written only when IA32_RTIT_CTL.TraceEn is 0; otherwise WRMSR causes a general-protection
fault (#GP). IA32_RTIT_CR3_MATCH[4:0] are reserved and must be 0; an attempt to set those bits using WRMSR
causes a #GP.
36.2.7.7 IA32_RTIT_OUTPUT_BASE MSR
This MSR is used to configure the trace output destination, when output is directed to memory
(IA32_RTIT_CTL.FabricEn = 0). The size of the address field is determined by the maximum physical address width
(MAXPHYADDR), as reported by CPUID.80000008H:EAX[7:0].
When the ToPA output scheme is used, the processor may update this MSR when packet generation is enabled, and
those updates are asynchronous to instruction execution. Therefore, the values in this MSR should be considered
unreliable unless packet generation is disabled (IA32_RTIT_CTL.TraceEn = 0).
Accesses to this MSR are supported only if Intel PT output to memory is supported, hence when either
CPUID.(EAX=14H, ECX=0):ECX[bit 0] or CPUID.(EAX=14H, ECX=0):ECX[bit 2] are set. Otherwise WRMSR or
RDMSR cause a general-protection fault (#GP). If supported, this MSR can be written only when
IA32_RTIT_CTL.TraceEn is 0; otherwise WRMSR causes a general-protection fault (#GP).