18-24 Vol. 3B

PERFORMANCE MONITORING

18.6.1.1   Processor Event Based Sampling (PEBS)

In the Silvermont microarchitecture, the PEBS facility can be used with precise events. PEBS is supported using 
IA32_PMC0 (see also Section 17.4.9). 
PEBS uses a debug store mechanism to store a set of architectural state information for the processor. The infor-
mation provides architectural state of the instruction executed after the instruction that caused the event (See 
Section 18.4.4). 
The list of precise events supported in the Silvermont microarchitecture is shown in Table 18-12.

Table 18-12.  PEBS Performance Events for the Silvermont Microarchitecture

Event Name

Event Select

Sub-event 

UMask

BR_INST_RETIRED

C4H

ALL_BRANCHES

00H

JCC

7EH

TAKEN_JCC

FEH

CALL

F9H

REL_CALL

FDH

IND_CALL

FBH

NON_RETURN_IND

EBH

FAR_BRANCH

BFH

RETURN

F7H

BR_MISP_RETIRED

C5H

ALL_BRANCHES

00H

JCC

7EH

TAKEN_JCC

FEH

IND_CALL

FBH

NON_RETURN_IND

EBH

RETURN

F7H

MEM_UOPS_RETIRED

04H

L2_HIT_LOADS

02H

L2_MISS_LOADS

04H

DLTB_MISS_LOADS

08H

HITM

20H

REHABQ

03H

LD_BLOCK_ST_FORWARD

01H

LD_SPLITS

08H