28-16 Vol. 3C

VMX SUPPORT FOR ADDRESS TRANSLATION

EP4TAs. (The instruction may also invalidate mappings associated with other VPIDs and for other linear 
addresses.)

— Single-context. If the INVVPID type is 1, the logical processor invalidates all linear mappings and 

combined mappings associated with the VPID specified in the INVVPID descriptor. Linear mappings and 
combined mappings for that VPID are invalidated for all PCIDs and, for combined mappings, all EP4TAs. 
(The instruction may also invalidate mappings associated with other VPIDs.)

— All-context. If the INVVPID type is 2, the logical processor invalidates linear mappings and combined 

mappings associated with all VPIDs except VPID 0000H and with all PCIDs. (The instruction may also 
invalidate linear mappings with VPID 0000H.) Combined mappings are invalidated for all EP4TAs.

— Single-context-retaining-globals. If the INVVPID type is 3, the logical processor invalidates linear 

mappings and combined mappings associated with the VPID specified in the INVVPID descriptor. Linear 
mappings and combined mappings for that VPID are invalidated for all PCIDs and, for combined mappings, 
all EP4TAs. The logical processor is not required to invalidate information that was used for global transla-
tions (although it may do so). See Section 4.10, “Caching Translation Information” for details regarding 
global translations. (The instruction may also invalidate mappings associated with other VPIDs.)

See Chapter 30 for details of the INVVPID instruction. See Section 28.3.3.3 for guidelines regarding use of this 
instruction.

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Execution of the INVEPT instruction invalidates guest-physical mappings and combined mappings. Invalidation 
is based on instruction operands, called the INVEPT type and the INVEPT descriptor. Two INVEPT types are 
currently defined:
— Single-context. If the INVEPT type is 1, the logical processor invalidates all guest-physical mappings and 

combined mappings associated with the EP4TA specified in the INVEPT descriptor. Combined mappings for 
that EP4TA are invalidated for all VPIDs and all PCIDs. (The instruction may invalidate mappings associated 
with other EP4TAs.)

— All-context. If the INVEPT type is 2, the logical processor invalidates guest-physical mappings and 

combined mappings associated with all EP4TAs (and, for combined mappings, for all VPIDs and PCIDs).

See Chapter 30 for details of the INVEPT instruction. See Section 28.3.3.4 for guidelines regarding use of this 
instruction.

•

A power-up or a reset invalidates all linear mappings, guest-physical mappings, and combined mappings.

28.3.3.2   Operations that Need Not Invalidate Cached Mappings

The following items detail cases of operations that are not required to invalidate certain cached mappings:

•

Operations that architecturally invalidate entries in the TLBs or paging-structure caches independent of VMX 
operation are not required to invalidate any guest-physical mappings.

•

The INVVPID instruction is not required to invalidate any guest-physical mappings.

•

The INVEPT instruction is not required to invalidate any linear mappings.

•

VMX transitions are not required to invalidate any guest-physical mappings. If the “enable VPID” VM-execution 
control is 1, VMX transitions are not required to invalidate any linear mappings or combined mappings. 

•

The VMXOFF and VMXON instructions are not required to invalidate any linear mappings, guest-physical 
mappings, or combined mappings.

A logical processor may invalidate any cached mappings at any time. For this reason, the operations identified 
above may invalidate the indicated mappings despite the fact that doing so is not required.

28.3.3.3   Guidelines for Use of the INVVPID Instruction

The need for VMM software to use the INVVPID instruction depends on how that software is virtualizing memory 
(e.g., see Section 32.3, “Memory Virtualization”). 
If EPT is not in use, it is likely that the VMM is virtualizing the guest paging structures. Such a VMM may configure 
the VMCS so that all or some of the operations that invalidate entries the TLBs and the paging-structure caches 
(e.g., the INVLPG instruction) cause VM exits. If VMM software is emulating these operations, it may be necessary