Vol. 3A 13-9

SYSTEM PROGRAMMING FOR INSTRUCTION SET EXTENSIONS AND PROCESSOR EXTENDED STATES

13.5.3 

Enable the Use Of XSAVE Feature Set And XSAVE State Components

Operating systems need to enable the use of XSAVE feature set by writing to CR4.OSXSAVE[bit 18] to enable 
XSETBV/XGETBV instructions to access XCR0 and to support processor extended state management using 
XSAVE/XRSTOR. When XSAVE feature set is enabled, all enumerated XSAVE sub features such as optimized save, 
compaction and supervisor state support are also enabled. Operating systems also need to enable the XSAVE state 
components in XCR0 using XSETBV instruction.
XSAVE state components can subsequently be disabled in XCR0. However, disabling state components of AVX or 
AVX-512 that are not in initial configuration may incur power and performance penalty on SSE and AVX instructions 
respectively. If AVX state is disabled when it is not in its initial configuration, subsequent SSE instructions may 
incur a penalty. If AVX-512 state is disabled when it is not in its initial configuration, subsequent SSE and AVX 
instructions may incur a penalty. It is recommended that the operating systems and VMM set AVX or AVX-512 state 
components to their initial configuration before disabling them. This can be achieved by one of the two methods 
below.

•

Using XRSTOR: Operating system or VMM can set the state of AVX or AVX-512 state components using XRSTOR 
instruction before disabling them in XCR0.

•

Using VZEROUPPER: Operating system or VMM can set AVX and AVX-512 state components to their initial 
configuration using VZEROUPPER instruction before disabling them in XCR0. Note that this will set both AVX 
and AVX-512 state components to their initial configuration. If the intent is to only disable AVX-512 state, 
Operating system or VMM will need to save AVX state before executing VZEROUPPER and restore it afterwards.

13.5.4 

Provide an Initialization for the XSAVE State Components

The XSAVE header of a newly allocated XSAVE area should be initialized to all zeroes before saving context. An 
operating system may choose to establish beginning state-component values for a task by executing XRSTOR from 
an XSAVE area that the OS has configured. If it is desired to begin state component i in its initial configuration, the 
OS should clear bit i in the XSTATE_BV field in the XSAVE header; otherwise, it should set that bit and place the 
desired beginning value in the appropriate location in the XSAVE area.
When a buffer is allocated for compacted size, software must ensure that the XCOMP_BV field is setup correctly 
before restoring from the buffer. Bit 63 of the XCOMP_BV field indicates that the save area is in the compacted 
format and the remaining bits indicate the states that have space allocated in the save area. If the buffer is first 
used to save the state in compacted format, then the save instructions will setup the XCOMP_BV field appropri-
ately. If the buffer is first used to restore the state, then software must set up the XCOMP_BV field.

13.5.5 

Providing the Required Exception Handlers

Instructions part of each XSAVE managed features may generate exceptions and operating system may need to 
enable such exceptions and provide handlers for them. Section 13.8 describes feature specific OS requirements for 
each XSAVE managed features.

13.6 

INTEROPERABILITY OF THE XSAVE FEATURE SET AND FXSAVE/FXRSTOR

The FXSAVE instruction writes x87 FPU and SSE state information to a 512-byte FXSAVE save area. FXRSTOR 
restores the processor’s x87 FPU and SSE states from an FXSAVE area. The XSAVE features set supports x87 FPU 
and SSE states using the same layout as the FXSAVE area to provide interoperability of FXSAVE versus XSAVE, and 
FXRSTOR versus XRSTOR. The XSAVE feature set allows system software to manage SSE state independent of x87 
FPU states. Thus system software that had been using FXSAVE and FXRSTOR to manage x87 FPU and SSE states 
can transition to using the XSAVE feature set to manage x87 FPU, SSE and other processor extended states in a 
systematic and forward-looking manner. See Section 10.5 and Chapter 13 of the Intel® 64 and IA-32 Architectures 
Software Developer’s Manual, Volume 1 for more details.
System software can implement forward-looking processor extended state management using the XSAVE feature 
set. In this case, system software must specify the bit vector mask in EDX:EAX appropriately when executing 
XSAVE/XRSTOR instructions.