INDEX
INDEX-12 Vol. 3D
description of
,
introduction of in IA-32 processors
,
introduction to
,
list of
,
machine-check architecture
,
P6 family processors
Pentium 4 processor
,
,
Pentium processors
reading and writing
,
,
reading & writing in 64-bit mode
,
virtualization support
,
VMX support
MSR_ TC_PRECISE_EVENT MSR
MSR_DEBUBCTLB MSR
,
,
,
MSR_DEBUGCTLA MSR
,
,
MSR_DEBUGCTLB MSR
,
,
,
,
,
,
MSR_EBC_FREQUENCY_ID MSR
MSR_EBC_HARD_POWERON MSR
,
MSR_EBC_SOFT_POWERON MSR
,
MSR_IFSB_CNTR7 MSR
,
MSR_IFSB_CTRL6 MSR
,
MSR_IFSB_DRDY0 MSR
MSR_IFSB_DRDY1 MSR
MSR_IFSB_IBUSQ0 MSR
MSR_IFSB_IBUSQ1 MSR
MSR_IFSB_ISNPQ0 MSR
MSR_IFSB_ISNPQ1 MSR
MSR_LASTBRANCH _TOS
,
MSR_LASTBRANCH_0_TO_IP
MSR_LASTBRANCH_n MSR
,
,
,
MSR_LASTBRANCH_n_FROM_IP MSR
,
,
,
MSR_LASTBRANCH_n_TO_IP MSR
,
MSR_LASTBRANCH_n_TO_LIP MSR
MSR_LASTBRANCH_TOS MSR
MSR_LER_FROM_LIP MSR
MSR_LER_TO_LIP MSR
,
,
MSR_PEBS_ MATRIX_VERT MSR
MSR_PEBS_MATRIX_VERT MSR
MSR_PLATFORM_BRV
,
MTRR feature flag, CPUID instruction
MTRRcap MSR
MTRRfix MSR
MTRRs
,
base & mask calculations
cache control
,
description of
,
,
dual-core processors
enabling caching
,
feature identification
,
fixed-range registers
IA32_MTRRCAP MSR
,
IA32_MTRR_DEF_TYPE MSR
initialization of
introduction of in IA-32 processors
,
introduction to
,
large page size considerations
,
logical processors
,
mapping physical memory with
,
memory types and their properties
MemTypeGet() function
MemTypeSet() function
multiple-processor considerations
,
precedence of cache controls
precedences
programming interface
remapping memory types
,
state of following a hardware reset
variable-range registers
,
Multi-core technology
Multiple-processor management
bus locking
,
guaranteed atomic operations
initialization
MP protocol
,
procedure
local APIC
,
memory ordering
,
MP protocol
,
overview of
,
SMM considerations
VMM design
,
asymmetric
,
CPUID emulation
,
external data structures
index-data registers
initialization
,
moving between processors
,
symmetric
,
Multiple-processor system
local APIC and I/O APICs, Pentium 4
,
local APIC and I/O APIC, P6 family
Multisegment model
Multitasking
initialization for
,
initializing IA-32e mode
,
linking tasks
,
mechanism, description of
overview
setting up TSS
,
setting up TSS descriptor
,
Multi-threading support
executing multiple threads
handling interrupts
logical processors per package
mapping resources
microcode updates
performance monitoring counters
programming considerations
See also: Hyper-Threading Technology and dual-core technology
MWAIT instruction
,
power management extensions
MXCSR register
,
N
NaN, compatibility, IA-32 processors
,
NE (numeric error) flag
CR0 control register
,
,
,
NEG instruction
NetBurst microarchitecture (see Intel NetBurst microarchitecture)
NMI interrupt
description of
handling during initialization
handling in SMM
handling multiple NMIs
masking
receiving when processor is shutdown
reference information
vector
NMI# pin
,
,
Nominal CPI method
Nonconforming code segments
accessing
C (conforming) flag
description of
Non-halted clockticks
setting up counters
,
Non-Halted CPI method
,