Vol. 3A 2-15

SYSTEM ARCHITECTURE OVERVIEW

WP

Write Protect (bit 16 of CR0) — When set, inhibits supervisor-level procedures from writing into read-
only pages; when clear, allows supervisor-level procedures to write into read-only pages (regardless of the 
U/S bit setting; see Section 4.1.3 and Section 4.6). This flag facilitates implementation of the copy-on-
write method of creating a new process (forking) used by operating systems such as UNIX.

NE

Numeric Error (bit 5 of CR0) — Enables the native (internal) mechanism for reporting x87 FPU errors 
when set; enables the PC-style x87 FPU error reporting mechanism when clear. When the NE flag is clear 
and the IGNNE# input is asserted, x87 FPU errors are ignored. When the NE flag is clear and the IGNNE# 
input is deasserted, an unmasked x87 FPU error causes the processor to assert the FERR# pin to generate 
an external interrupt and to stop instruction execution immediately before executing the next waiting 
floating-point instruction or WAIT/FWAIT instruction. 
The FERR# pin is intended to drive an input to an external interrupt controller (the FERR# pin emulates the 
ERROR# pin of the Intel 287 and Intel 387 DX math coprocessors). The NE flag, IGNNE# pin, and FERR# 
pin are used with external logic to implement PC-style error reporting. Using FERR# and IGNNE# to handle 
floating-point exceptions is deprecated by modern operating systems; this non-native approach also limits 
newer processors to operate with one logical processor active.
See also: Section 8.7, “Handling x87 FPU Exceptions in Software” in Chapter 8, “Programming with the x87 
FPU,” and Appendix A, “EFLAGS Cross-Reference,” in the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 1.

ET

Extension Type (bit 4 of CR0) — Reserved in the Pentium 4, Intel Xeon, P6 family, and Pentium proces-
sors. In the Pentium 4, Intel Xeon, and P6 family processors, this flag is hardcoded to 1. In the Intel386 
and Intel486 processors, this flag indicates support of Intel 387 DX math coprocessor instructions when 
set.

TS

Task Switched (bit 3 of CR0) — Allows the saving of the x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 
context on a task switch to be delayed until an x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instruction is 
actually executed by the new task. The processor sets this flag on every task switch and tests it when 
executing x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instructions.

•

If the TS flag is set and the EM flag (bit 2 of CR0) is clear, a device-not-available exception (#NM) is 

raised prior to the execution of any x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instruction; with the 
exception of PAUSE, PREFETCHh, SFENCE, LFENCE, MFENCE, MOVNTI, CLFLUSH, CRC32, and POPCNT. 
See the paragraph below for the special case of the WAIT/FWAIT instructions.

•

If the TS flag is set and the MP flag (bit 1 of CR0) and EM flag are clear, an #NM exception is not raised 

prior to the execution of an x87 FPU WAIT/FWAIT instruction.

•

If the EM flag is set, the setting of the TS flag has no effect on the execution of x87 

FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instructions.

Table 2-2 shows the actions taken when the processor encounters an x87 FPU instruction based on the 
settings of the TS, EM, and MP flags. Table 12-1 and 13-1 show the actions taken when the processor 
encounters an MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instruction.

The processor does not automatically save the context of the x87 FPU, XMM, and MXCSR registers on a 
task switch. Instead, it sets the TS flag, which causes the processor to raise an #NM exception whenever 
it encounters an x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instruction in the instruction stream for the 
new task (with the exception of the instructions listed above). 
The fault handler for the #NM exception can then be used to clear the TS flag (with the CLTS instruction) 
and save the context of the x87 FPU, XMM, and MXCSR registers. If the task never encounters an x87 
FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instruction, the x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 
context is never saved.