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DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES

allows single-stepping the processor on taken branches. See Section 17.4.3, “Single-Stepping on
Branches,” for more information about the BTF flag.

— TR (trace message enable) flag (bit 6) — When set, branch trace messages are enabled. When the

processor detects a taken branch, interrupt, or exception; it sends the branch record out on the system bus
as a branch trace message (BTM). See Section 17.4.4, “Branch Trace Messages,” for more information
about the TR flag.

— BTS (branch trace store) flag (bit 7) — When set, the flag enables BTS facilities to log BTMs to a

memory-resident BTS buffer that is part of the DS save area. See Section 17.4.9, “BTS and DS Save Area.”

— BTINT (branch trace interrupt) flag (bits 8) — When set, the BTS facilities generate an interrupt when

the BTS buffer is full. When clear, BTMs are logged to the BTS buffer in a circular fashion. See Section 17.4.5,
“Branch Trace Store (BTS),” for a description of this mechanism.

•

Debug store (DS) feature flag (bit 21), returned by the CPUID instruction — Indicates that the
processor provides the debug store (DS) mechanism, which allows BTMs to be stored in a memory-resident
BTS buffer. See Section 17.4.5, “Branch Trace Store (BTS).”

•

Last Branch Record (LBR) Stack — The LBR stack consists of 8 MSRs (MSR_LASTBRANCH_0 through
MSR_LASTBRANCH_7); bits 31-0 hold the ‘from’ address, bits 63-32 hold the ‘to’ address (MSR addresses start
at 40H). See Figure 17-15.

•

Last Branch Record Top-of-Stack (TOS) Pointer — The TOS Pointer MSR contains a 3-bit pointer (bits 2-0)
to the MSR in the LBR stack that contains the most recent branch, interrupt, or exception recorded. For Intel
Core Solo and Intel Core Duo processors, this MSR is located at register address 01C9H.

For compatibility, the Intel Core Solo and Intel Core Duo processors provide two 32-bit MSRs (the
MSR_LER_TO_LIP and the MSR_LER_FROM_LIP MSRs) that duplicate functions of the LastExceptionToIP and Last-
ExceptionFromIP MSRs found in P6 family processors.
For details, see Section 17.10, “Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based
on Skylake Microarchitecture,” and Section 35.19, “MSRs In Intel

Figure 17-14. IA32_DEBUGCTL MSR for Intel Core Solo

and Intel Core

Duo Processors

Figure 17-15. LBR Branch Record Layout for the Intel Core Solo

and Intel

Core Duo Processor