Vol. 3C 35-63

MODEL-SPECIFIC REGISTERS (MSRS)

When this bit is clear (0, default), the processor does not change 

the VID signals or the bus to core ratio when the processor enters 

a thermally managed state. 
The BIOS must enable this feature if the TM2 feature flag 

(CPUID.1:ECX[8]) is set; if the TM2 feature flag is not set, this 

feature is not supported and BIOS must not alter the contents of 

the TM2 bit location. 
The processor is operating out of specification if both this bit and 

the TM1 bit are set to 0.

15:14

Reserved.

16

Shared

Enhanced Intel SpeedStep Technology Enable (R/W) 
See Table 35-2.

18

Shared

ENABLE MONITOR FSM (R/W) 
See Table 35-2.

19

Reserved.

20

Shared

Enhanced Intel SpeedStep Technology Select Lock (R/WO)
When set, this bit causes the following bits to become read-only:
• Enhanced Intel SpeedStep Technology Select Lock (this bit), 

• Enhanced Intel SpeedStep Technology Enable bit.

The bit must be set before an Enhanced Intel SpeedStep 

Technology transition is requested. This bit is cleared on reset.

21

Reserved.

22

Unique

Limit CPUID Maxval (R/W) 
See Table 35-2.

23

Shared

xTPR Message Disable (R/W) 
See Table 35-2.

33:24

Reserved.

34

Unique

XD Bit Disable (R/W) 
See Table 35-2.

63:35

Reserved.

1C9H

457

MSR_LASTBRANCH_TOS

Unique

Last Branch Record Stack TOS (R/W) 
Contains an index (bits 0-2) that points to the MSR containing the 

most recent branch record.
See MSR_LASTBRANCH_0_FROM_IP (at 40H).

1D9H

473

IA32_DEBUGCTL

Unique

Debug Control (R/W) 
See Table 35-2.

1DDH

477

MSR_LER_FROM_LIP Unique

Last Exception Record From Linear IP (R) 
Contains a pointer to the last branch instruction that the processor 

executed prior to the last exception that was generated or the last 

interrupt that was handled.

Table 35-4.  MSRs in 45 nm and 32 nm Intel® Atom™ Processor Family (Contd.)

Register 

Address

Register Name

Shared/

Unique

Bit Description

 Hex

Dec