Page 1972

INDEX

INDEX-8 Vol. 3D

IA32_VMX_CR0_FIXED1 MSR

IA32_VMX_CR4_FIXED0 MSR

IA32_VMX_CR4_FIXED1 MSR

IA32_VMX_ENTRY_CTLS MSR

IA32_VMX_EXIT_CTLS MSR

IA32_VMX_MISC MSR

IA32_VMX_PINBASED_CTLS MSR

IA32_VMX_PROCBASED_CTLS MSR

IA32_VMX_VMCS_ENUM MSR

35-299

A-7

ICR

Interrupt Command Register

10-37

10-41

10-46

ID (identification) flag

EFLAGS register

IDIV instruction

IDT

64-bit mode

6-16

call interrupt & exception-handlers from

6-11

change base & limit in real-address mode

20-5

description of

6-9

handling NMIs during initialization

9-9

initializing protected-mode operation

9-10

initializing real-address mode operation

introduction to

limit

paging of

structure in real-address mode

20-5

task switching

7-10

task-gate descriptor

7-8

types of descriptors allowed

6-10

use in real-address mode

20-4

IDTR register

description of

IA-32e mode

introduction to

limit

loading in real-address mode

20-5

storing

3-16

IE (invalid operation exception) flag

x87 FPU status word

22-8

IEEE Standard 754 for Binary Floating-Point Arithmetic

IF (interrupt enable) flag

EFLAGS register

IN instruction

INC instruction

Index field, segment selector

3-7

INIT interrupt

10-3

Initial-count register, local APIC

10-16

Initialization

built-in self-test (BIST)

9-1

9-5

CS register state following

9-5

EIP register state following

9-5

example

9-14

first instruction executed

hardware reset

IA-32e mode

IDT, protected mode

IDT, real-address mode

9-8

Intel486 SX processor and Intel 487 SX math coprocessor

22-15

location of software-initialization code

9-5

machine-check initialization

15-18

model and stepping information

9-5

multitasking environment

overview

paging

processor state after reset

protected mode

real-address mode

RESET# pin

setting up exception- and interrupt-handling facilities

x87 FPU

INIT# pin

INIT# signal

INS instruction

Instruction operands

Instruction-breakpoint exception condition

17-8

Instructions

new instructions

22-4

obsolete instructions

privileged

serializing

supported in real-address mode

20-3

system

2-7

2-20

INS/INSB/INSW/INSD instruction

INT 3 instruction

INT instruction

INT n instruction

INT (APIC interrupt enable) flag, PerfEvtSel0 and PerfEvtSel1 MSRs (P6

family processors)

18-4

18-117

INT15 and microcode updates

9-42

INT3 instruction

3-9

6-4

Intel 287 math coprocessor

22-7

Intel 387 math coprocessor system

22-7

Intel 487 SX math coprocessor

22-6

22-15

Intel 64 architecture

definition of

1-3

relation to IA-32

1-3

Intel 8086 processor

22-7

Intel Core Solo and Duo processors

model-specific registers

35-304

Intel Core Solo and Intel Core Duo processors

event mask (Umask)

18-15

18-16

last branch, interrupt, exception recording

17-35

notes on P-state transitions

14-1

performance monitoring

18-15

18-16

performance monitoring events

sub-fields layouts

time stamp counters

Intel NetBurst microarchitecture

1-2

Intel software network link

1-10

Intel SpeedStep Technology

See: Enhanced Intel SpeedStep Technology

Intel VTune Performance Analyzer

related information

1-9

Intel Xeon processor

1-1

last branch, interrupt, and exception recording

17-32

time-stamp counter

17-40

Intel Xeon processor MP

with 8MB L3 cache

18-107

18-109

Intel286 processor

22-7

Intel386 DX processor

22-7

Intel386 SL processor

2-7

Intel486 DX processor

22-6

Intel486 SX processor

22-6

22-15

Interprivilege level calls

call mechanism

5-15

stack switching

5-17

Interprocessor interrupt (IPIs)

10-1

Interprocessor interrupt (IPI)

in MP systems

10-1

interrupt

6-12

Interrupt Command Register

10-37

Interrupt command register (ICR), local APIC

10-18

Interrupt gates