35-66 Vol. 3C

MODEL-SPECIFIC REGISTERS (MSRS)

412H

1042

IA32_MC4_ADDR

Shared

See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC4_ADDR register is either not implemented or 

contains no address if the ADDRV flag in the MSR_MC4_STATUS 

register is clear. 
When not implemented in the processor, all reads and writes to this 

MSR will cause a general-protection exception.

480H

1152

IA32_VMX_BASIC

Unique

Reporting Register of Basic VMX Capabilities (R/O) 
See Table 35-2.
See Appendix A.1, “Basic VMX Information.”

481H

1153

IA32_VMX_PINBASED_

CTLS

Unique

Capability Reporting Register of Pin-based VM-execution 

Controls (R/O) 
See Table 35-2.
See Appendix A.3, “VM-Execution Controls.”

482H

1154

IA32_VMX_PROCBASED_

CTLS

Unique

Capability Reporting Register of Primary Processor-based 

VM-execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls.”

483H

1155

IA32_VMX_EXIT_CTLS

Unique

Capability Reporting Register of VM-exit Controls (R/O) 
See Table 35-2.
See Appendix A.4, “VM-Exit Controls.”

484H

1156

IA32_VMX_ENTRY_CTLS

Unique

Capability Reporting Register of VM-entry Controls (R/O) 
See Table 35-2.
See Appendix A.5, “VM-Entry Controls.”

485H

1157

IA32_VMX_MISC

Unique

Reporting Register of Miscellaneous VMX Capabilities (R/O) 
See Table 35-2.
See Appendix A.6, “Miscellaneous Data.”

486H

1158

IA32_VMX_CR0_FIXED0

Unique

Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) 
See Table 35-2.
See Appendix A.7, “VMX-Fixed Bits in CR0.”

487H

1159

IA32_VMX_CR0_FIXED1

Unique

Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) 
See Table 35-2.
See Appendix A.7, “VMX-Fixed Bits in CR0.”

488H

1160

IA32_VMX_CR4_FIXED0

Unique

Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) 
See Table 35-2.
See Appendix A.8, “VMX-Fixed Bits in CR4.”

489H

1161

IA32_VMX_CR4_FIXED1

Unique

Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) 
See Table 35-2.
See Appendix A.8, “VMX-Fixed Bits in CR4.”

48AH

1162

IA32_VMX_VMCS_ENUM

Unique

Capability Reporting Register of VMCS Field Enumeration (R/O)
See Table 35-2.
See Appendix A.9, “VMCS Enumeration.”

Table 35-4.  MSRs in 45 nm and 32 nm Intel® Atom™ Processor Family (Contd.)

Register 

Address

Register Name

Shared/

Unique

Bit Description

 Hex

Dec