35-120 Vol. 3C

MODEL-SPECIFIC REGISTERS (MSRS)

486H

1158

IA32_VMX_CR0_FIXED0

Thread

Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) 
See Table 35-2.
See Appendix A.7, “VMX-Fixed Bits in CR0.”

487H

1159

IA32_VMX_CR0_FIXED1

Thread

Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) 
See Table 35-2.
See Appendix A.7, “VMX-Fixed Bits in CR0.”

488H

1160

IA32_VMX_CR4_FIXED0

Thread

Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) 
See Table 35-2.
See Appendix A.8, “VMX-Fixed Bits in CR4.”

489H

1161

IA32_VMX_CR4_FIXED1

Thread

Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) 
See Table 35-2.
See Appendix A.8, “VMX-Fixed Bits in CR4.”

48AH

1162

IA32_VMX_VMCS_ENUM

Thread

Capability Reporting Register of VMCS Field Enumeration 

(R/O). 
See Table 35-2.
See Appendix A.9, “VMCS Enumeration.”

48BH

1163

IA32_VMX_PROCBASED_

CTLS2

Thread

Capability Reporting Register of Secondary Processor-based 

VM-execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls.”

600H

1536

IA32_DS_AREA

Thread

DS Save Area (R/W)
See Table 35-2.
See Section 18.12.4, “Debug Store (DS) Mechanism.”

680H

1664

MSR_

LASTBRANCH_0_FROM_IP

Thread

Last Branch Record 0 From IP (R/W)
One of sixteen pairs of last branch record registers on the last 

branch record stack. The From_IP part of the stack contains 

pointers to the source instruction. See also:
• Last Branch Record Stack TOS at 1C9H

• Section 17.7.1 and record format in Section 17.4.8.1

681H

1665

MSR_

LASTBRANCH_1_FROM_IP

Thread

Last Branch Record 1 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.

682H

1666

MSR_

LASTBRANCH_2_FROM_IP

Thread

Last Branch Record 2 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP. 

683H

1667

MSR_

LASTBRANCH_3_FROM_IP

Thread

Last Branch Record 3 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.

684H

1668

MSR_

LASTBRANCH_4_FROM_IP

Thread

Last Branch Record 4 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.

685H

1669

MSR_

LASTBRANCH_5_FROM_IP

Thread

Last Branch Record 5 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.

686H

1670

MSR_

LASTBRANCH_6_FROM_IP

Thread

Last Branch Record 6 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.

Table 35-13.  MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)

Register 

Address

Register Name

Scope

Bit Description

 Hex

Dec