35-312 Vol. 3C

MODEL-SPECIFIC REGISTERS (MSRS)

481H

1153

IA32_VMX_PINBASED_

CTLS

Unique

Capability Reporting Register of Pin-based VM-execution 

Controls (R/O)
See Appendix A.3, “VM-Execution Controls”
(If CPUID.01H:ECX.[bit 9])

482H

1154

IA32_VMX_PROCBASED_

CTLS

Unique

Capability Reporting Register of Primary Processor-based 

VM-execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls”
(If CPUID.01H:ECX.[bit 9])

483H

1155

IA32_VMX_EXIT_CTLS

Unique

Capability Reporting Register of VM-exit Controls (R/O)
See Appendix A.4, “VM-Exit Controls”
(If CPUID.01H:ECX.[bit 9])

484H

1156

IA32_VMX_ENTRY_CTLS

Unique

Capability Reporting Register of VM-entry Controls (R/O)
See Appendix A.5, “VM-Entry Controls”
(If CPUID.01H:ECX.[bit 9])

485H

1157

IA32_VMX_MISC

Unique

Reporting Register of Miscellaneous VMX Capabilities (R/O)
See Appendix A.6, “Miscellaneous Data”
(If CPUID.01H:ECX.[bit 9])

486H

1158

IA32_VMX_CR0_FIXED0

Unique

Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)
See Appendix A.7, “VMX-Fixed Bits in CR0”
(If CPUID.01H:ECX.[bit 9])

487H

1159

IA32_VMX_CR0_FIXED1

Unique

Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)
See Appendix A.7, “VMX-Fixed Bits in CR0”
(If CPUID.01H:ECX.[bit 9])

488H

1160

IA32_VMX_CR4_FIXED0

Unique

Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)
See Appendix A.8, “VMX-Fixed Bits in CR4”
(If CPUID.01H:ECX.[bit 9])

489H

1161

IA32_VMX_CR4_FIXED1

Unique

Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)
See Appendix A.8, “VMX-Fixed Bits in CR4”
(If CPUID.01H:ECX.[bit 9])

48AH

1162

IA32_VMX_VMCS_ENUM

Unique

Capability Reporting Register of VMCS Field Enumeration (R/O)
See Appendix A.9, “VMCS Enumeration”
(If CPUID.01H:ECX.[bit 9])

48BH

1163

IA32_VMX_PROCBASED_

CTLS2

Unique

Capability Reporting Register of Secondary Processor-based 

VM-execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls”
(If CPUID.01H:ECX.[bit 9] and 

IA32_VMX_PROCBASED_CTLS[bit 63])

600H

1536

IA32_DS_AREA

Unique

DS Save Area (R/W) 
See Table 35-2.
See Section 18.12.4, “Debug Store (DS) Mechanism.”

Table 35-44.  MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV 

Register 

Address

Register Name

Shared/

Unique

Bit Description

 Hex

Dec