35-298 Vol. 3C
MODEL-SPECIFIC REGISTERS (MSRS)
40FH
1039 IA32_MC3_MISC
0, 1, 2, 3,
4, 6
Shared
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
The IA32_MC3_MISC MSR is either not
implemented or does not contain additional
information if the MISCV flag in the
IA32_MC3_STATUS register is clear.
When not implemented in the processor, all reads
and writes to this MSR will cause a general-
protection exception.
410H
1040 IA32_MC4_CTL
0, 1, 2, 3,
4, 6
Shared
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
411H
1041 IA32_MC4_STATUS
0, 1, 2, 3,
4, 6
Shared
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
412H
1042 IA32_MC4_ADDR
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC2_ADDR register is either not
implemented or contains no address if the ADDRV
flag in the IA32_MC4_STATUS register is clear.
When not implemented in the processor, all reads
and writes to this MSR will cause a general-
protection exception.
413H
1043 IA32_MC4_MISC
See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
The IA32_MC2_MISC MSR is either not
implemented or does not contain additional
information if the MISCV flag in the
IA32_MC4_STATUS register is clear.
When not implemented in the processor, all reads
and writes to this MSR will cause a general-
protection exception.
480H 1152
IA32_VMX_BASIC
3, 4, 6
Unique
Reporting Register of Basic VMX Capabilities
(R/O)
See Table 35-2.
See Appendix A.1, “Basic VMX Information.”
481H 1153
IA32_VMX_PINBASED_CTLS
3, 4, 6
Unique
Capability Reporting Register of Pin-based
VM-execution Controls (R/O)
See Table 35-2.
See Appendix A.3, “VM-Execution Controls.”
482H 1154
IA32_VMX_PROCBASED_CTLS
3, 4, 6
Unique
Capability Reporting Register of Primary
Processor-based VM-execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls,” and
483H 1155
IA32_VMX_EXIT_CTLS
3, 4, 6
Unique
Capability Reporting Register of VM-exit
Controls (R/O)
See Appendix A.4, “VM-Exit Controls,” and see
Table 35-41. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register
Address
Register Name
Fields and Flags
Model
Avail-
ability
Shared/
Unique
1
Bit Description
Hex
Dec