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35-274 Vol. 3C

MODEL-SPECIFIC REGISTERS (MSRS)

488H

1160

IA32_VMX_CR4_FIXED0

Core

Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) 
See Table 35-2.

489H

1161

IA32_VMX_CR4_FIXED1

Core

Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) 
See Table 35-2.

48AH

1162

IA32_VMX_VMCS_ENUM

Core

Capability Reporting Register of VMCS Field Enumeration (R/O)
See Table 35-2.

48BH

1163

IA32_VMX_PROCBASED_

CTLS2

Core

Capability Reporting Register of Secondary Processor-based 

VM-execution Controls (R/O)
See Table 35-2

48CH

1164

IA32_VMX_EPT_VPID_ENU

M

Core

Capability Reporting Register of EPT and VPID (R/O) 
See Table 35-2

48DH

1165

IA32_VMX_TRUE_PINBASE

D_CTLS

Core

Capability Reporting Register of Pin-based VM-execution Flex 

Controls (R/O)
See Table 35-2

48EH

1166

IA32_VMX_TRUE_PROCBAS

ED_CTLS

Core

Capability Reporting Register of Primary Processor-based 

VM-execution Flex Controls (R/O)
See Table 35-2

48FH

1167

IA32_VMX_TRUE_EXIT_CTL

S

Core

Capability Reporting Register of VM-exit Flex Controls (R/O)
See Table 35-2

490H

1168

IA32_VMX_TRUE_ENTRY_C

TLS

Core

Capability Reporting Register of VM-entry Flex Controls (R/O)
See Table 35-2

491H

1169

IA32_VMX_FMFUNC

Core

Capability Reporting Register of VM-function Controls (R/O)
See Table 35-2

4C1H

1217

IA32_A_PMC0

Thread

See Table 35-2.

4C2H

1218

IA32_A_PMC1

Thread

See Table 35-2.

600H

1536

IA32_DS_AREA

Thread

DS Save Area (R/W)
See Table 35-2.

606H

1542

MSR_RAPL_POWER_UNIT

Package

Unit Multipliers used in RAPL Interfaces (R/O) 

3:0

Package

Power Units
See Section 14.9.1, “RAPL Interfaces.”

7:4

Package

Reserved

12:8

Package

Energy Status Units
Energy related information (in Joules) is based on the multiplier, 

1/2^ESU; where ESU is an unsigned integer represented by bits 

12:8. Default value is 0EH (or 61 micro-joules)

15:13

Package

Reserved

19:16

Package

Time Units
See Section 14.9.1, “RAPL Interfaces.”

63:20

Reserved

Table 35-40.  Selected MSRs Supported by Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signature 

06_57H

Address

Register Name

Scope

Bit Description

 Hex

Dec