2-10 Vol. 3A

SYSTEM ARCHITECTURE OVERVIEW

POPF, POPFD, or IRET instruction, a debug exception is generated after the instruction that follows the 
POPF, POPFD, or IRET.

IF

Interrupt enable (bit 9) — Controls the response of the processor to maskable hardware interrupt 
requests (see also: Section 6.3.2, “Maskable Hardware Interrupts”). The flag is set to respond to maskable 
hardware interrupts; cleared to inhibit maskable hardware interrupts. The IF flag does not affect the gener-
ation of exceptions or nonmaskable interrupts (NMI interrupts). The CPL, IOPL, and the state of the VME 
flag in control register CR4 determine whether the IF flag can be modified by the CLI, STI, POPF, POPFD, 
and IRET.

IOPL

I/O privilege level field (bits 12 and 13) — Indicates the I/O privilege level (IOPL) of the currently 
running program or task. The CPL of the currently running program or task must be less than or equal to 
the IOPL to access the I/O address space. The POPF and IRET instructions can modify this field only when 
operating at a CPL of 0. 
The IOPL is also one of the mechanisms that controls the modification of the IF flag and the handling of 
interrupts in virtual-8086 mode when virtual mode extensions are in effect (when CR4.VME = 1). See also: 
Chapter 18, “Input/Output,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
Volume 1.

NT

Nested task (bit 14) — Controls the chaining of interrupted and called tasks. The processor sets this flag 
on calls to a task initiated with a CALL instruction, an interrupt, or an exception. It examines and modifies 
this flag on returns from a task initiated with the IRET instruction. The flag can be explicitly set or cleared 
with the POPF/POPFD instructions; however, changing to the state of this flag can generate unexpected 
exceptions in application programs. 
See also: Section 7.4, “Task Linking.”

RF

Resume (bit 16) — Controls the processor’s response to instruction-breakpoint conditions. When set, this 
flag temporarily disables debug exceptions (#DB) from being generated for instruction breakpoints 
(although other exception conditions can cause an exception to be generated). When clear, instruction 
breakpoints will generate debug exceptions. 
The primary function of the RF flag is to allow the restarting of an instruction following a debug exception 
that was caused by an instruction breakpoint condition. Here, debug software must set this flag in the 
EFLAGS image on the stack just prior to returning to the interrupted program with IRETD (to prevent the 
instruction breakpoint from causing another debug exception). The processor then automatically clears 
this flag after the instruction returned to has been successfully executed, enabling instruction breakpoint 
faults again.
See also: Section 17.3.1.1, “Instruction-Breakpoint Exception Condition.”

VM

Virtual-8086 mode (bit 17) — Set to enable virtual-8086 mode; clear to return to protected mode. 

Figure 2-5.  System Flags in the EFLAGS Register

31

22 21 20 19 18 17 16

R

F

I

D

A

C

V
M

VM — Virtual-8086 Mode

RF — Resume Flag
NT — Nested Task Flag
IOPL— I/O Privilege Level
IF

— Interrupt Enable Flag

AC — Alignment Check / Access Control

ID

— Identification Flag

VIP — Virtual Interrupt Pending

15

13

14

12 11 10 9 8 7 6 5 4 3 2 1 0

0

C

F

A
F

P

F 1

D

F

I

F

T
F

S
F

Z
F

N

T

0

0

V

I

P

V

I

F

O

F

I

O
P

L

VIF — Virtual Interrupt Flag

TF

— Trap Flag

Reserved

Reserved (set to 0)