INDEX
INDEX-10 Vol. 3D
description of
,
,
record stack
,
,
,
,
,
,
,
record top-of-stack pointer
,
,
,
LastBranchFromIP MSR
LastBranchToIP MSR
LastExceptionFromIP MSR
,
LastExceptionToIP MSR
,
LBR (last branch/interrupt/exception) flag, DEBUGCTLMSR MSR
,
,
LDR
Logical Destination Register
,
LDS instruction
LDT
associated with a task
,
description of
,
,
index into with index field of segment selector
pointer to in TSS
pointers to exception and interrupt handlers
segment descriptors in
segment selector field, TSS
selecting with TI (table indicator) flag of segment selector
setting up during initialization
,
task switching
task-gate descriptor
,
use in address translation
,
LDTR register
description of
,
,
,
IA-32e mode
,
limit
,
storing
,
LE (local exact breakpoint enable) flag, DR7 register
,
LEN0-LEN3 (Length) fields, DR7 register
,
LES instruction
,
LFENCE instruction
,
,
,
LFS instruction
LGDT instruction
,
,
,
LGS instruction
,
,
LIDT instruction
,
,
,
Limit checking
description of
,
pointer offsets are within limits
,
Limit field, segment descriptor
Linear address
description of
,
IA-32e mode
,
introduction to
,
Linear address space
defined
,
of task
Link (to previous task) field, TSS
,
Linking tasks
mechanism
,
modifying task linkages
,
LINT pins
function of
LLDT instruction
,
,
LMSW instruction
,
Local APIC
,
64-bit mode
APIC_ID value
arbitration over the APIC bus
arbitration over the system bus
,
block diagram
,
cluster model
CR8 usage
,
current-count register
,
description of
,
detecting with CPUID
,
DFR (destination format register)
,
divide configuration register
,
enabling and disabling
,
external interrupts
features
Pentium 4 and Intel Xeon
Pentium and P6
focus processor
,
global enable flag
IA32_APIC_BASE MSR
,
initial-count register
internal error interrupts
interrupt command register (ICR)
,
interrupt destination
interrupt distribution mechanism
,
interrupt sources
IRR (interrupt request register)
I/O APIC
,
local APIC and 82489DX
local APIC and I/O APIC
,
local vector table (LVT)
,
logical destination mode
LVT (local-APIC version register)
,
mapping of resources
,
MDA (message destination address)
,
overview of
,
performance-monitoring counter
,
physical destination mode
receiving external interrupts
register address map
,
shared resources
,
SMI interrupt
spurious interrupt
spurious-interrupt vector register
,
state after a software (INIT) reset
,
state after INIT-deassert message
,
state after power-up reset
state of
,
SVR (spurious-interrupt vector register)
,
timer
,
timer generated interrupts
,
TMR (trigger mode register)
,
valid interrupts
,
version register
,
Local descriptor table register (see LDTR)
Local descriptor table (see LDT)
Local vector table (LVT)
description of
thermal entry
,
Local x2APIC
,
Local xAPIC ID
LOCK prefix
,
,
,
,
Locked (atomic) operations
automatic bus locking
bus locking
,
effects on caches
loading a segment descriptor
on IA-32 processors
overview of
,
software-controlled bus locking
LOCK# signal
,
Logical address
description of
IA-32e mode
Logical address space, of task
,
Logical destination mode, local APIC
,
Logical processors
per physical package
Logical x2APIC ID
low-temperature interrupt enable bit
LSL instruction
,
LSS instruction
,
,
LTR instruction
,