10-2 Vol. 3A

ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)

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APIC internal error interrupts — When an error condition is recognized within the local APIC (such as an 
attempt to access an unimplemented register), the APIC can be programmed to send an interrupt to its 
associated processor (see Section 10.5.3, “Error Handling”).

Of these interrupt sources: the processor’s LINT0 and LINT1 pins, the APIC timer, the performance-monitoring 
counters, the thermal sensor, and the internal APIC error detector are referred to as local interrupt sources. 
Upon receiving a signal from a local interrupt source, the local APIC delivers the interrupt to the processor core 
using an interrupt delivery protocol that has been set up through a group of APIC registers called the local vector 
table or LVT (see Section 10.5.1, “Local Vector Table”). A separate entry is provided in the local vector table for 
each local interrupt source, which allows a specific interrupt delivery protocol to be set up for each source. For 
example, if the LINT1 pin is going to be used as an NMI pin, the LINT1 entry in the local vector table can be set up 
to deliver an interrupt with vector number 2 (NMI interrupt) to the processor core.
The local APIC handles interrupts from the other two interrupt sources (externally connected I/O devices and IPIs) 
through its IPI message handling facilities. 
A processor can generate IPIs by programming the interrupt command register (ICR) in its local APIC (see Section 
10.6.1, “Interrupt Command Register (ICR)”). The act of writing to the ICR causes an IPI message to be generated 
and issued on the system bus (for Pentium 4 and Intel Xeon processors) or on the APIC bus (for Pentium and P6 
family processors). See Section 10.2, “System Bus Vs. APIC Bus.”
IPIs can be sent to other processors in the system or to the originating processor (self-interrupts). When the target 
processor receives an IPI message, its local APIC handles the message automatically (using information included 
in the message such as vector number and trigger mode). See Section 10.6, “Issuing Interprocessor Interrupts,” 
for a detailed explanation of the local APIC’s IPI message delivery and acceptance mechanism.
The local APIC can also receive interrupts from externally connected devices through the I/O APIC (see 
Figure 10-1). The I/O APIC is responsible for receiving interrupts generated by system hardware and I/O devices 
and forwarding them to the local APIC as interrupt messages.

Individual pins on the I/O APIC can be programmed to generate a specific interrupt vector when asserted. The I/O 
APIC also has a “virtual wire mode” that allows it to communicate with a standard 8259A-style external interrupt 
controller. Note that the local APIC can be disabled (see Section 10.4.3, “Enabling or Disabling the Local APIC”). 
This allows an associated processor core to receive interrupts directly from an 8259A interrupt controller.

 

Figure 10-1.  Relationship of Local APIC and I/O APIC In Single-Processor Systems

I/O APIC

External

Interrupts

System Chip Set

System Bus

Processor Core

Local APIC

Pentium 4 and 

Local

Interrupts

Bridge

PCI

Intel Xeon Processors

I/O APIC

External

Interrupts

System Chip Set

3-Wire APIC Bus

Processor Core

Local APIC

Pentium and P6

Local

Interrupts

Family Processors

Interrupt

Messages

Interrupt

Messages

Interrupt

Messages