INDEX
INDEX-14 Vol. 3D
PC0 and PC1 (pin control) fields, CESR MSR (Pentium processor)
,
PCD pin (Pentium processor)
,
PCD (page-level cache disable) flag
CR3 control register
,
,
page-directory entries
page-table entries
,
,
,
PCE (performance monitoring counter enable) flag, CR4 control register
,
,
,
PCE (performance-monitoring counter enable) flag, CR4 control register
,
PDBR (see CR3 control register)
PE (protection enable) flag, CR0 control register
,
,
PEBS records
,
PEBS (precise event-based sampling) facilities
availability of
,
description of
,
DS save area
IA-32e mode
,
PEBS buffer
,
PEBS records
,
,
writing a PEBS interrupt service routine
writing interrupt service routine
,
PEBS_UNAVAILABLE flag
IA32_MISC_ENABLE MSR
Pentium 4 processor
compatibility with FP software
last branch, interrupt, and exception recording
,
list of performance-monitoring events
MSRs supported
,
,
,
,
time-stamp counter
Pentium II processor
,
Pentium III processor
Pentium M processor
last branch, interrupt, and exception recording
,
MSRs supported by
time-stamp counter
Pentium Pro processor
Pentium processor
,
compatibility with MCA
list of performance-monitoring events
MSR supported by
,
performance-monitoring counters
,
PerfCtr0 and PerfCtr1 MSRs
(P6 family processors)
,
,
PerfEvtSel0 and PerfEvtSel1 MSRs
(P6 family processors)
,
PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family processors)
Performance events
architectural
Intel Core Solo and Intel Core Duo processors
,
non-architectural
non-retirement events (Pentium 4 processor)
P6 family processors
Pentium 4 and Intel Xeon processors
,
Pentium M processors
Pentium processor
Performance state
Performance-monitoring counters
counted events (P6 family processors)
counted events (Pentium 4 processor)
,
counted events (Pentium processors)
description of
,
events that can be counted (Pentium processors)
,
interrupt
,
introduction of in IA-32 processors
,
monitoring counter overflow (P6 family processors)
,
overflow, monitoring (P6 family processors)
,
overview of
P6 family processors
Pentium II processor
,
Pentium Pro processor
,
Pentium processor
reading
,
setting up (P6 family processors)
,
software drivers for
starting and stopping
,
PG (paging) flag
CR0 control register
,
PG (paging) flag, CR0 control register
,
,
PGE (page global enable) flag, CR4 control register
,
,
PhysBase field, IA32_MTRR_PHYSBASEn MTRR
,
,
Physical address extension
introduction to
Physical address space
4 GBytes
64 GBytes
addressing
,
defined
description of
guest and host spaces
,
IA-32e mode
mapped to a task
,
mapping with variable-range MTRRs
,
,
memory virtualization
,
Physical destination mode, local APIC
PhysMask
IA32_MTRR_PHYSMASKn MTRR
PM0/BP0 and PM1/BP1 (performance-monitor) pins (Pentium processor)
,
PML4 tables
,
Pointers
code-segment pointer size
,
limit checking
validation
,
POP instruction
POPF instruction
,
,
Power consumption
software controlled clock
,
,
Precise event-based sampling (see PEBS)
PREFETCHh instruction
,
Previous task link field, TSS
,
,
Privilege levels
checking when accessing data segments
checking, for call gates
,
checking, when transferring program control between code segments
,
description of
protection rings
Privileged instructions
,
Processor families
06H
0FH
,
Processor management
initialization
,
local APIC
,
microcode update facilities
,
overview of
,
See also: multiple-processor management
Processor ordering, description of
,
PROCHOT# log
,
,
PROCHOT# or FORCEPR# event bit
,
,
Protected mode
IDT initialization
,
initialization for
,
mixing 16-bit and 32-bit code modules
,
mode switching
PE flag, CR0 register
,
switching to
,
,
system data structures required during initialization
,
Protection