17-18 Vol. 3B

DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES

The DS save area is divided into three parts (see Figure 17-5): buffer management area, branch trace store (BTS) 
buffer, and PEBS buffer. The buffer management area is used to define the location and size of the BTS and PEBS 
buffers. The processor then uses the buffer management area to keep track of the branch and/or PEBS records in 
their respective buffers and to record the performance counter reset value. The linear address of the first byte of 
the DS buffer management area is specified with the IA32_DS_AREA MSR.
The fields in the buffer management area are as follows: 

•

BTS buffer base — Linear address of the first byte of the BTS buffer. This address should point to a natural 
doubleword boundary.

•

BTS index — Linear address of the first byte of the next BTS record to be written to. Initially, this address 
should be the same as the address in the BTS buffer base field.

•

BTS absolute maximum — Linear address of the next byte past the end of the BTS buffer. This address should 
be a multiple of the BTS record size (12 bytes) plus 1.

•

BTS interrupt threshold — Linear address of the BTS record on which an interrupt is to be generated. This 
address must point to an offset from the BTS buffer base that is a multiple of the BTS record size. Also, it must 
be several records short of the BTS absolute maximum address to allow a pending interrupt to be handled prior 
to processor writing the BTS absolute maximum record.

•

PEBS buffer base — Linear address of the first byte of the PEBS buffer. This address should point to a natural 
doubleword boundary.

•

PEBS index — Linear address of the first byte of the next PEBS record to be written to. Initially, this address 
should be the same as the address in the PEBS buffer base field.

•

PEBS absolute maximum — Linear address of the next byte past the end of the PEBS buffer. This address 
should be a multiple of the PEBS record size (40 bytes) plus 1.

•

PEBS interrupt threshold — Linear address of the PEBS record on which an interrupt is to be generated. This 
address must point to an offset from the PEBS buffer base that is a multiple of the PEBS record size. Also, it 
must be several records short of the PEBS absolute maximum address to allow a pending interrupt to be 
handled prior to processor writing the PEBS absolute maximum record.

•

PEBS counter reset value — A 40-bit value that the counter is to be reset to after state information has 
collected following counter overflow. This value allows state information to be collected after a preset number 
of events have been counted.