Vol. 3C 35-287

MODEL-SPECIFIC REGISTERS (MSRS)

When this flag is set and the processor is in the 

stop-clock state (STPCLK# is asserted), asserting 

the FERR# pin signals to the processor that an 

interrupt (such as, INIT#, BINIT#, INTR, NMI, SMI#, 

or RESET#) is pending and that the processor 

should return to normal operation to handle the 

interrupt.
This flag does not affect the normal operation of 

the FERR# pin (to indicate an unmasked floating-

point error) when the STPCLK# pin is not 

asserted.

11

Branch Trace Storage Unavailable 

(BTS_UNAVILABLE) (R)
See Table 35-2.
When set, the processor does not support branch 

trace storage (BTS); when clear, BTS is supported.

12

PEBS_UNAVILABLE: Processor Event Based 

Sampling Unavailable (R)
See Table 35-2.
When set, the processor does not support 

processor event-based sampling (PEBS); when 

clear, PEBS is supported.

13

3

TM2 Enable (R/W)
When this bit is set (1) and the thermal sensor 

indicates that the die temperature is at the pre-

determined threshold, the Thermal Monitor 2 

mechanism is engaged. TM2 will reduce the bus to 

core ratio and voltage according to the value last 

written to MSR_THERM2_CTL bits 15:0.
When this bit is clear (0, default), the processor 

does not change the VID signals or the bus to core 

ratio when the processor enters a thermal 

managed state.
If the TM2 feature flag (ECX[8]) is not set to 1 

after executing CPUID with EAX = 1, then this 

feature is not supported and BIOS must not alter 

the contents of this bit location. The processor is 

operating out of spec if both this bit and the TM1 

bit are set to disabled states.

17:14

Reserved.

18 

3, 4, 6

ENABLE MONITOR FSM (R/W)
See Table 35-2.

19

Adjacent Cache Line Prefetch Disable (R/W) 
When set to 1, the processor fetches the cache 

line of the 128-byte sector containing currently 

required data. When set to 0, the processor 

fetches both cache lines in the sector.

Table 35-41.  MSRs in the Pentium® 4 and Intel® Xeon® Processors  (Contd.)

Register 

Address

Register Name

Fields and Flags

Model 

Avail-

ability

Shared/

Unique

1

Bit Description

 Hex

Dec